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8-bit flash mcu with op amps & comparators HT45F23A revision: v1.00 date: ???? 0 ?? ? 01 ? ???? 0 ?? ? 01 ?
rev. 1.00 ? ???? 0 ?? ? 01 ? rev. 1.00 ? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators table of contents eates cpu feat ? res ......................................................................................................................... 7 periphera ? feat ? res ................................................................................................................. 8 genera? description ......................................................................................... 9 b?ock diagram ................................................................................................ 10 pin assignment ........... .................................................................................... 11 pin description .......... ..................................................................................... 11 abso??te maxim?m ratings .......................................................................... 14 d.c. characteristics ....................................................................................... 14 a.c. characteristics ....................................................................................... 17 op amplifer electrical characteristics comparator electrical characteristics c ? ocking and pipe ? ining ......................................................................................................... ? 0 program co ? nter ................................................................................................................... ? 1 stack ..................................................................................................................................... ?? arithmetic and logic unit C alu ........................................................................................... ?? f?ash program memor? ................................................................................. ?? str ? ct ? re ................................................................................................................................ ?? specia ? vectors ..................................................................................................................... ?? look- ? p tab ? e ............. ........................................................................................................... ? 4 tab ? e program examp ? e ........................................................................................................ ? 5 in circ ? it programming ......................................................................................................... ? 6 ram data memor? ......................................................................................... ?7 str ? ct ? re ................................................................................................................................ ? 7 specia ? f ? nction registers ................................................................................................... ? 8 indirect addressing registers C iar0 ? iar1 ......................................................................... ? 8 memor ? pointers C mp0 ? mp1 .............................................................................................. ? 9 bank pointer bp .................................................................................................................... ? 0 acc ? m ?? ator C acc ............................................................................................................... ? 0 program co ? nter low register C pcl .................................................................................. ? 0 look- ? p tab ? e registers C tblp ? tblh ................................................................................ ? 0 stat ? s register C status .................................................................................................... ? 1 eeprom data memory eeprom data memor ? str ? ct ? re ........................................................................................ ?? eeprom registers ............ .................................................................................................. ??
rev. 1.00 ? ???? 0?? ?01? rev. 1.00 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators reading data from the eeprom ......................................................................................... ?? writing data to the eeprom ................................................................................................ ? 4 write protection ..................................................................................................................... ? 4 eeprom interr ? pt ............. ................................................................................................... ? 4 programming considerations ............. ................................................................................... ? 4 programming examp ? es ........................................................................................................ ? 5 oscillator ........................................................................................................ 36 osci ?? ator overview ............. .................................................................................................. ? 6 system clock confgurations ................................................................................................ ? 6 externa ? cr ? sta ? /ceramic osci ?? ator C hxt ........................................................................... ? 7 externa ? rc osci ?? ator C erc ............. .................................................................................. ? 7 externa ? osci ?? ator C ec ........................................................................................................ ? 8 interna ? rc osci ?? ator C hirc ............. .................................................................................. ? 8 externa ? ?? .768khz cr ? sta ? osci ?? ator C lxt ............. ........................................................... ? 8 lxt osci ?? ator low power f ? nction ...................................................................................... ? 9 interna ? ?? khz osci ?? ator C lirc ........................................................................................... ? 9 s ? pp ? ementar ? osci ?? ators .................................................................................................... 40 operating modes and system clocks ......................................................... 40 s ? stem c ? ocks ...................................................................................................................... 40 s ? stem operation modes ...................................................................................................... 40 contro ? register .................................................................................................................... 4 ? fast wake- ? p ........................................................................................................................ 44 operating mode switching and wake- ? p .............................................................................. 44 normal mode to slow mode switching ........................................................................... 45 slow mode to normal mode switching ........................................................................... 47 entering the sleep0 mode .................................................................................................. 47 entering the sleep1 mode .................................................................................................. 47 entering the idle0 mode ...................................................................................................... 48 entering the idle1 mode ...................................................................................................... 48 standb ? c ? rrent considerations ........................................................................................... 48 wake- ? p ................................................................................................................................ 49 programming considerations ............. ................................................................................... 49 watchdog timer ........... .................................................................................. 50 watchdog timer c ? ock so ? rce .............................................................................................. 50 watchdog timer contro ? register ............. ............................................................................ 50 watchdog timer operation ................................................................................................... 51 reset and initialisation .................................................................................. 52 reset f ? nctions ............. ....................................................................................................... 5 ? reset initia ? conditions ......................................................................................................... 54 input/output ports ......................................................................................... 57 p ??? -high resistors ................................................................................................................ 57 port a wake- ? p ............. ........................................................................................................ 58 i/o port contro ? registers ..................................................................................................... 58
rev. 1.00 4 ???? 0 ?? ? 01 ? rev. 1.00 5 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators port b nmos open drain contro ? register .......................................................................... 59 i/o pin str ? ct ? res .................................................................................................................. 59 programming considerations ............. ................................................................................... 59 timer/event counters ................................................................................... 60 &rjuljwkh7lphu(yhw&rwhu,sw&orfn6rufh .................................................... 61 timer registers C tmr0 ? tmr1l ? tmr1h ........................................................................... 61 timer contro ? registers C tmr0c ? tmr1c .......................................................................... 6 ? rq?xulq?wkh7lphu0rgh .................................................................................................. 6 ? rq?xulq?wkh(yhqwrxqwhu0rgh .................................................................................... 6 ? rq?xulq?wkh?xovh:lgwk0hdvxuhphqw0rgh ................................................................. 64 programmab ? e freq ? enc ? divider pfd ................................................................................ 65 presca ? er ............................................................................................................................... 66 i/o interfacing ........................................................................................................................ 67 timer/event co ? nter pins interna ? fi ? ter ............................................................................... 68 programming considerations ............. ................................................................................... 68 timer program examp ? e ....................................................................................................... 69 pulse width modulator .................................................................................. 70 pwm operation ..................................................................................................................... 70 6+ ? pwm mode .................................................................................................................... 71 7+1 pwm mode .................................................................................................................... 7 ? pwm o ? tp ? t contro ? ............................................................................................................. 7 ? analog to digital converter .......... ................................................................ 73 a/d overview ............. ........................................................................................................... 7 ? a/d converter register description ...................................................................................... 7 ? a/d converter data registers C adrl ? adrh ..................................................................... 74 a/d converter contro ? registers C adcr ? acsr ? adpcr .................................................. 74 a/d operation ....................................................................................................................... 77 a/d inp ? t pins ............. .......................................................................................................... 78 s ? mmar ? of a/d conversion steps ............. .......................................................................... 78 programming considerations ............. ................................................................................... 79 a/d transfer f ? nction ............. .............................................................................................. 79 a/d programming examp ? e ................................................................................................... 81 serial interface module C sim ....................................................................... 83 spi interface ......................................................................................................................... 8 ? spi registers ............. ........................................................................................................... 84 spi comm ? nication .............................................................................................................. 87 i ? c interface ............ .............................................................................................................. 89 i ? c registers ......................................................................................................................... 89 i ? c b ? s comm ? nication ........................................................................................................ 9 ? i ? c b ? s start signa ? ............................................................................................................... 94 s ? ave address ....................................................................................................................... 94 i ? c b ? s read/write signa ? .................................................................................................... 95 i ? c b ? s s ? ave address acknow ? edge signa ? ......................................................................... 95 i ? c b ? s data and acknow ? edge signa ? ............ ..................................................................... 95
rev. 1.00 4 ???? 0?? ?01? rev. 1.00 5 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators peripheral clock output ........... ..................................................................... 97 periphera ? c ? ock operation ............. ...................................................................................... 97 scom function for lcd ................................................................................ 98 lcd operation ............. ......................................................................................................... 98 lcd bias contro ? .................................................................................................................. 99 ldo f ? nction ...................................................................................................................... 100 operational amplifers .......... ...................................................................... 101 2shudwlrdopsolhu5hjlvwhuv ............. .............................................................................. 101 ?shudwlrqdopsolhu?shudwlrq ............. ............................................................................. 104 ?shudwlrqdopsolhu)xqfwlrqv ............. ............................................................................. 104 comparators ................................................................................................ 107 comparator operation ........................................................................................................ 107 comparator registers ......................................................................................................... 107 comparator f ? nctions ............. ............................................................................................ 109 interrupts ....................................................................................................... 111 interr ? pt register ................................................................................................................. 111 interr ? pt operation ............................................................................................................... 11 ? interr ? pt priorit ? .................................................................................................................... 11 ? externa ? interr ? pt ............. ..................................................................................................... 115 externa ? periphera ? interr ? pt ............. ................................................................................... 117 timer/event co ? nter interr ? pt .............................................................................................. 117 spi/i ? c interface interr ? pt .................................................................................................... 117 m ?? ti-f ? nction interr ? pt ......................................................................................................... 118 a/d interr ? pt ......................................................................................................................... 118 time base interr ? pt .............................................................................................................. 118 comparator interr ? pt ............................................................................................................ 119 eeprominterr ? pt ............. .................................................................................................. 1 ? 0 lvd interr ? pt ....................................................................................................................... 1 ? 0 interr ? pt wake- ? p f ? nction ................................................................................................. 1 ? 0 programming considerations ............. ................................................................................. 1 ? 0 buzzer ........................................................................................................... 121 power down mode and wake-up ................................................................ 123 entering the idle or sleep mode ............. ........................................................................ 1 ?? standb ? c ? rrent considerations ......................................................................................... 1 ?? wake- ? p .............................................................................................................................. 1 ?? low voltage detector C lvd .......... ............................................................. 124 lvd register ............. .......................................................................................................... 1 ? 4 lvd operation ..................................................................................................................... 1 ? 5 voice output ................................................................................................. 126 voice contro ? ....................................................................................................................... 1 ? 6 a ? dio o ? tp ? t and vo ?? me contro ? C dal ? dah ? dactrl ................................................. 1 ? 6 confguration options ................................................................................. 127
rev. 1.00 6 ???? 0 ?? ? 01 ? rev. 1.00 7 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators application circuits ........... .......................................................................... 128 instruction set .............................................................................................. 129 introd ? ction ......................................................................................................................... 1 ? 9 instr ? ction timing ................................................................................................................ 1 ? 9 moving and transferring data ............................................................................................. 1 ? 9 arithmetic operations .......................................................................................................... 1 ? 9 logica ? and rotate operation ............................................................................................. 1 ? 0 branches and contro ? transfer ........................................................................................... 1 ? 0 bit operations ..................................................................................................................... 1 ? 0 tab ? e read operations ....................................................................................................... 1 ? 0 other operations ............. .................................................................................................... 1 ? 0 instruction set summary .......... .................................................................. 131 tab ? e conventions ............................................................................................................... 1 ? 1 instruction defnition ................................................................................... 133 package information ................................................................................... 142 16-pin nsop (150mi ? ) o ? t ? ine dimensions ......................................................................... 14 ? ? 0-pin ssop (150mi ? ) o ? t ? ine dimensions ......................................................................... 14 ? ? 4-pin ssop (150mi ? ) o ? t ? ine dimensions ......................................................................... 144 product tape and reel specifcations ....................................................... 145 ree ? dimensions ................................................................................................................. 145 carrier tape dimensions ..................................................................................................... 146
rev. 1.00 6 ???? 0?? ?01? rev. 1.00 7 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators features cpu features ? operating voltage: C f sys = 32.768khz: 2.2v~5.5v C f sys = 910k hz: 2.2v~5.5v C f sys = 2 mhz: 2.2v~5.5v C f sys = 4mhz: 2.2v~5.5v C f sys = 8mhz: 3.3v~5.5v ? tinypower technology for low power operation ? power down and wake-up functions to reduce power consumption ? oscillator types: C external crystal - hxt C external 32.768khz crystal - lxt C external rc - erc C internal rc - hirc C internal 32khz rc - lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 32khz, 910khz, 2mhz, 4mhz and 8mhz oscillator requires no external components ? externally supplied system clock option ? all instructions executed in one or two machine cycles ? table read instructions ? 61 or 63 powerful instructions ? 6-level subroutine nesting ? bit manipulation instruction
rev. 1.00 8 ???? 0 ?? ? 01 ? rev. 1.00 9 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators peripheral features ? flash program memory: 2k15 ? ram data memory: 1288 ? eeprom data memory: 648 ? watchdog t imer function ? up to 22 bidirectional i/o lines ? software controlled 4-scom lines lcd com driver with 1/2 bias ? multiple pin-shared external interrupts ? single 8-bit programmable t imer/event counter with overfow interrupt and single 16-bit programmable t imer/event counter with overfow interrupt function ? dual t ime-base functions ? serial interfaces module - sim for spi or i 2 c ? dual comparator functions ? dual operational amplifers functions ? operational amplifer output to internal two channel 12-bit adc function ? up to 6 channel 12-bit adc ? up to 2 channel 8-bit pwm ? 12-bit audio dac output ? pfd/buzzer for audio frequency generation ? internal 2.4v/3.3v ldo ? low voltage reset function ? low voltage detect function ? 16-pin nsop, 20/24-pin ssop package types
rev. 1.00 8 ???? 0?? ?01? rev. 1.00 9 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators general description the HT45F23A is a flash memory t inypower a/d type 8-bit high performance risc architecture microcontrollers, designed especially for applications that interface directly to analog signals. the HT45F23A device has a higher gain bandwidth making it more suitable for higher frequency applications. offering u sers t he c onvenience o f fl ash me mory m ulti-programming f eatures, t he d evice a lso include s a wi de ra nge of func tions a nd fe atures. ot her m emory i ncludes a n a rea of ram da ta memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include an integrated multi-channel analog to digital converter , dual pulse width modulation outputs, dual operational amplifers , dual comparators , one internal 2.4v or 3.3v ldo (low drop out) for voltage regulator and a 12-bit dac for voice output application, communication wi th t he ou tside worl d i s c atered fo r by i ncluding fu lly i ntegrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal w atchdog timer, low v oltage reset and low v oltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , lxt , erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the unique holtek t inypower techn ology also gives the device extremely low current consumption characteristics, an extremely important consideration in the present trend for low power battery powered applicati ons. the usual holtek mcu features such as power down and wake-up functions, oscillator options, programmable frequency divider , etc. combine to ensure user applications require a minimum of external components. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vice wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving, home security systems related to smoke detector and many others.
rev. 1.00 10 ???? 0 ?? ? 01 ? rev. 1.00 11 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators block diagram the following block diagram illustrates the main functional blocks.
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rev. 1.00 10 ???? 0?? ?01? rev. 1.00 11 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators pin assignment

pin description pin name function opt i/t o/t description pa0/cnp/ scom0 pa0 papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p ? wake- ? p. cnp cmp1c1 cmpi comparator inp ? t pin scom0 lcdc scom software contro ?? ed 1/ ? bias lcd com pa1/c1out/ tc0 pa1 papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p ? wake- ? p. c1out cmp1c1 cmpo comparator 1 o ? tp ? t pin tc0 st externa ? timer 0 c ? ock inp ? t pa ? /a1p/ c ? out pa ? papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p ? wake- ? p. a1p opa1c1 opai opa1 non-inverting inp ? t pin c ? out cmp ? c1 cmpo comparator ? o ? tp ? t pin pa ? /a1n/int0 pa ? papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p ? wake- ? p. a1n opa1c1 opai opa1 inverting inp ? t pin int0 st externa ? interr ? pt 0 inp ? t pin pa4/a1e/t c1 pa4 papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and wake- ? p. a1e opa1c1 opao opa1 o ? tp ? t pin tc1 st externa ? timer 1 c ? ock inp ? t
rev. 1.00 1 ? ???? 0 ?? ? 01 ? rev. 1.00 1? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators pin name function opt i/t o/t description pa5/a ? p/pfd pa5 papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and wake- ? p. a ? p opa ? c1 opai opa ? non-inverting inp ? t pin pfd misc cmos pfd o ? tp ? t pa6/a ? n/bz pa6 papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and wake- ? p. a ? n opa ? c1 opai opa ? inverting inp ? t pin bz bpctl cmos b ? zzer o ? tp ? t pa7/a ? e/bz pa7 papu pawu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and wake- ? p. a ? e opa ? c1 opao opa ? o ? tp ? t pin bz bpctl cmos comp ? ementar ? b ? zzer o ? tp ? t pb0/sdo/int1 pb0 pbpu misc st cmos nmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and o ? tp ? t nmos str ? ct ? re. sdo cmos spi data o ? tp ? t int1 st externa ? interr ? pt 1 inp ? t pin pb1/sdi/sda pb1 pbpu misc st cmos nmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and o ? tp ? t nmos str ? ct ? re. sdi st spi data inp ? t sda st nmos i ? c data pb ? /sck/scl pb ? pbpu misc st cmos nmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and o ? tp ? t nmos str ? ct ? re. sck st spi seria ? c ? ock scl st nmos i ? c c ? ock pb ? /an0/ scs pb ? pbpu misc st cmos nmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p and o ? tp ? t nmos str ? ct ? re. an0 adcr an a/d channe ? 0 scs st spi s ? ave se ? ect pb4/an1/aud/ pck pb4 pbpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p an1 adcr an cmos a/d channe ? 1 aud dactrl d/a o ? tp ? t pin pck cmos periphera ? c ? ock o ? tp ? t pb5/an ? / pint pb5 pbpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p an ? adcr an a/d channe ? ? pint st periphera ? interr ? pt pb6/an ? / res pb6 pbpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p an ? adcr an a/d channe ? ? res co st reset pin pc0/an4/ osc ? pc0 pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. an4 adcr an a/d channe ? 4 osc ? co hxt hxt pin pc1/an5/ osc1 pc1 pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. an5 adcr an a/d channe ? 5 osc1 co hxt hxt/erc pin
rev. 1.00 1? ???? 0?? ?01? rev. 1.00 1 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators pin name function opt i/t o/t description pc ? / xt1 pc ? pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. xt1 co lxt lxt pin pc ? / xt ? pc ? pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. xt ? co lxt lxt pin pc4/vref/ vcap/scom1 pc4 pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. vref acsr an adc reference inp ? t vcap ldoc ldo o ? tp ? t capacitor pin. connect a 0.1f capacitor. scom1 lcdc scom software contro ?? ed 1/ ? bias lcd com pc5/pwm0/ c1n/s com ? pc5 pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. pwm0 bpctl cmos pwm0 o ? tp ? t pin c1n cmp1c1 cmpi comparator 1 inverting inp ? t pin scom ? lcdc scom software contro ?? ed 1/ ? bias lcd com pc6/pwm1/ c ? p/ s com ? pc6 pcpu st cmos genera ? p ? rpose i/o. register enab ? ed p ??? - ? p. pwm1 bpctl cmos pwm1 o ? tp ? t pin c ? p cmp ? c1 cmpi comparator ? non-inverting inp ? t pin scom ? lcdc scom software contro ?? ed 1/ ? bias lcd com vdd vdd pwr power s ? pp ?? vss vss pwr gro ? nd note: i/t: input type o/t: output type opt: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt t rigger input cmos: cmos output scom: software controlled lcd com hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator opai: operational amplifer input opao: operational amplifer output cmpi: comparator input cmpo: comparator output dao: d/a output
rev. 1.00 14 ???? 0 ?? ? 01 ? rev. 1.00 15 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. .................................................................................................................... -100ma i ol t otal .............. ..................................................................................................................... 100ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating vo ? tage f sys =910k hz ? (hxt/erc/hirc) ? . ? 5.5 v f sys = ? mhz ? (hxt/erc/hirc) ? . ? 5.5 v f sys =4mhz ? (hxt/erc/hirc/ec) ? . ? 5.5 v f sys =8mhz (hxt/erc/hirc/ec) ? . ? 5.5 v i dd1 operating c ? rrent (hxt ? erc) ? . ? v no ? oad ? f sys =f m =455khz ? adc off ? lvr off ? comparator off ? opas off 70 110 a operating c ? rrent (hxt ? erc) no ? oad ? f sys =f m = 455khz ? adc off ? lvr on ? comparator on ? opas off 100 150 a i dd ? operating c ? rrent (erc ? hirc) ? . ? v no ? oad ? f m =910khz ? f sys =f slow =455khz ? adc off ? lvr off ? comparator off ? opas off 90 1 ? 5 a operating c ? rrent (erc ? hirc) no ? oad ? f m =910khz ? f sys =f slow =455khz ? adc off ? lvr on ? comparator on ? opas off 1 ? 0 180 a i dd ? operating c ? rrent (erc ? hirc) ? . ? v no ? oad ? f sys =f m =910khz ? adc off ? lvr off ? comparator off ? opas off 110 170 a operating c ? rrent (erc ? hirc) no ? oad ? f sys =f m =910khz ? adc off ? lvr on ? comparator on ? opas off 160 ? 40 a
rev. 1.00 14 ???? 0?? ?01? rev. 1.00 15 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators symbol parameter test conditions min. typ. max. unit v dd conditions i dd4 operating c ? rrent (hxt ? erc) ? . ? v no ? oad ? f sys =f m =1mhz ? adc off ? lvr off ? comparator off ? opas off 1 ? 0 180 a operating c ? rrent (hxt ? erc) no ? oad ? f sys =f m =1mhz ? adc off ? lvr on ? comparator on ? opas off 170 ? 60 a i dd5 operating c ? rrent (hxt ? erc ? hirc) ? . ? v no ? oad ? f sys =f m = ? mhz ? adc off ? lvr off ? comparator off ? opas off 170 ? 60 a operating c ? rrent (hxt ? erc ? hirc) no ? oad ? f sys =f m = ? mhz ? adc off ? lvr on ? comparator on ? opas off ? 00 ? 00 a i dd6 operating c ? rrent (hxt ? erc ? hirc) ? v no ? oad ? f sys =f m =4mhz ? adc off 4 ? 0 6 ? 0 a 5v 700 1000 a i dd7 operating c ? rrent (hxt ? erc ? hirc) 5v no ? oad ? f sys =f m =8mhz ? adc off 1.5 ? .0 ma i dd9 operating c ? rrent (s ? ow mode ? f m =4mhz) (hxt ? erc ? hirc) ? v no ? oad ? f sys =f slow =1mhz ? adc off ? 00 ? 00 a 5v 400 600 a i dd10 operating c ? rrent (s ? ow mode ? f m =4mhz) (hxt ? erc ? hirc) ? v no ? oad ? f sys =f slow = ? mhz ? adc off ? 50 ? 75 a 5v 560 840 a i dd1 1 operating c ? rrent (s ? ow mode ? f m =8mhz) (hxt ? erc ? hirc) ? v no ? oad ? f sys =f slow = ? mhz ? adc off ? 00 450 a 5v 680 10 ? 0 a i dd1 ? operating c ? rrent (s ? ow mode ? f m =8mhz) (hxt ? erc ? hirc) ? v no ? oad ? f sys =f slow =4mhz ? adc off 450 800 a 5v 1000 1500 a i dd1 ? operating c ? rrent (f sys =lxt (note 1) or lirc) ? v no ? oad ? wdt off ? adc off 10 ? 0 a 5v ? 0 ? 5 a i stb1 standb ? c ? rrent (s ? eep) (f sys ? f sub ? f s ? f wdt =off ) ? v no ? oad ? s ? stem halt ? wdt off 0.1 1.0 a 5v 0. ? ? .0 a i stb ? standb ? c ? rrent (s ? eep) (f sys off; f s on; f wdt =f sub =lxt (note 1) or lirc) ? v no ? oad ? s ? stem halt ? wdt on ? 4 a 5v 4 6 a i stb ? standb ? c ? rrent (id ? e) (f sys off; f wdt off; f s =f sub =lxt (note 1) or lirc) ? v no ? oad ? s ? stem halt ? wdt off 4 6 a 5v 6 9 a i stb4 standb ? c ? rrent (id ? e) (f sys on ? f sys =f m =4mhz; f wdt off; f s =f sub =lxt (note 1) or lirc) ? v no ? oad ? s ? stem halt ? wdt off ? spi or i ? c on ? pclk on ? pclk=f sys /8 ? 6 0 ? 5 0 a 5v ? 50 660 a v il1 inp ? t low vo ? ta ge for i/o ? t mr n and intn 0 0. ? v dd v v ih1 inp ? t high vo ? tage for i/o ? tmrn and intn 0.7v dd v dd v v il ? inp ? t low vo ? tage ( res) 0 0.4v dd v v ih ? inp ? t high vo ? tage ( res) 0.9v dd v dd v v il ? inp ? t low vo ? tage (pb1~pb ? ) 5v 1 v v ih ? inp ? t high vo ? tage (pb1~pb ? ) 5v ? v v lvr1 low vo ? tage reset v lvr = ? .10v -5% t ? p. ? .10 +5% t ? p. v v lvr ? v lvr = ? .55v ? .55 v lvr ? v lvr = ? .15v ? .15 v lvr4 v lvr =4. ? 0v 4. ? 0
rev. 1.00 16 ???? 0 ?? ? 01 ? rev. 1.00 17 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators symbol parameter test conditions min. typ. max. unit v dd conditions v lvd1 low vo ? tage detector vo ? tage lvden=1 ? v lvd = ? .0v -5% t ? p. ? .0 +5% t ? p. v v lvd ? lvden=1 ? v lvd = ? . ? v ? . ? v lvd ? lvden=1 ? v lvd = ? .4v ? .4 v lvd4 lvden=1 ? v lvd = ? .7v ? .7 v lvd5 lvden=1 ? v lvd = ? .0v ? .0 v lvd6 lvden=1 ? v lvd = ? . ? v ? . ? v lvd7 lvden=1 ? v lvd = ? .6v ? .6 v lvd8 lvden=1 ? v lvd =4.4v 4.4 i ol i/o port sink c ? rrent ? v v ol =0.1v dd 6 1 ? ma 5v 10 ? 5 ma i oh i/o port so ? rce c ? rrent ? v v oh =0.9v dd - ? -4 ma 5v -5 -8 ma r ph p ??? -high resistance ? v 40 60 80 k 5v 10 ? 0 50 k av dd a/d converter operating vo ? tage ? .7 5.5 v v ad a/d inp ? t vo ? tage 0 v ref v v ref a/d inp ? t reference vo ? tage range av dd =5v ? v dd v dnl adc differentia ? non-linearit ? ? v v ref =v dd ? t ad =1s 1 ? lsb 5v inl adc integra ? non-linearit ? ? v v ref =v dd ? t ad =1s ? 4 lsb 5v i adc additiona ? power cons ? mption if a/d converter is used ? v 0.5 1.0 ma 5v 1.5 ? .0 ma v bg bandgap reference with b ? ffer vo ? tage - ? % 1. ? 5 + ? % v i lvr dc c ? rrent when lvr or lvd t ? rn on ? v 10 15 a 5v ? 0 ? 0 a v scom v dd / ? vo ? tage for lcd com 5v no ? oad 0.475 0.500 0.5 ? 5 vdd v ldo / ? vo ? tage for lcd com 5v no ? oad 0.475 0.500 0.5 ? 5 vldo i dd q ? iescent c ? rrent 5v no ? oad ? a1oen/a ? oen fxed to 0 1 ? 0 a i out o ? tp ? t c ? rrent 5v isel=0 ? lcdbuf=disab ? e 10 a isel=1 ? lcdbuf=disab ? e ? 5 a isel=0 ? lcdbuf=enab ? e ? ma isel=1 ? lcdbuf=enab ? e ? ma 1rwh w sys sys sub sub s uu
rev. 1.00 16 ???? 0?? ?01? rev. 1.00 17 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators a.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 s ? stem c ? ock (hxt ? erc ? hirc) ? . ? v~5.5v 400 4000 khz ? . ? v~5.5v 400 8000 khz f sys ? 8mhz hirc ? . ? v ta=25?c - ? % 8 + ? % mhz ? . ? v ta=-40?c~85?c -5% 8 +5% mhz ? .7v~5.5v ta=-40?c~85?c -10% 8 +10% mhz f sys ? 4mhz hirc ? . ? v ta=25?c - ? % 4 + ? % mhz ? . ? v ta=-40?c~85?c -5% 4 +5% mhz ? .7v~5.5v ta=-40?c~85?c -10% 4 +10% mhz f sys4 ? mhz hirc ? . ? v ta=25?c - ? % ? + ? % mhz ? . ? v ta=-40?c~85?c -5% ? +5% mhz ? .7v~5.5v ta=-40?c~85?c -10% ? +10% mhz f sys5 910khz hirc ? . ? v ta=25?c - ? % 0.91 + ? % mhz ? . ? v ta=-40?c~85?c -5% 0.91 +5% mhz ? .7v~5.5v ta=-40?c~85?c -10% 0.91 +10% mhz f lxt s ? stem c ? ock (lxt) ?? .768 khz f erc 4mhz erc (note ? ) ? . ? v r=150k, ta=25?c - ? % 4 + ? % mhz ? . ? v r=150k, ta=-40?c~85?c -8% 4 +8% mhz ? .7v~5.5v r=150k, ta=-40?c~85?c -15% 4 +15% mhz t lirc ?? khz rc period ? v ? 8.10 ? 1. ? 5 ? 4.40 s t res externa ? reset low p ?? se width 1 s t lvr low vo ? tage width to reset 60 1 ? 0 ? 4 0 s t lvd low vo ? tage width to interr ? pt 1 ? t sub t lvds lvdo stab ? e time 5v lvr disab ? e ? lvd enab ? e ? vbg is read ? 100 s t sst1 s ? stem start- ? p timer period (w/o fast start- ? p) of hxt/tbc power ? p or wake- ? p from s ? eep mode 10 ? 4 t sys * (note 1) t sst ? s ? stem start- ? p timer period of erc ? hirc ? ec power ? p or wake- ? p from halt (id ? e or s ? eep mode) 1 ? t sys t sst ? s ? stem start- ? p timer period (with fast start- ? p) of hxt/tbc wake- ? p from id ? e mode (f sl =f tbc) 1 ? t tbc (note ? ) t sst4 s ? stem start- ? p timer period (with fast start- ? p) of hxt/tbc wake- ? p from id ? e mode (f sl =f lirc ) 1 ? t lirc t int interr ? pt p ?? se width 1 s t ad a/d c ? ock period 0.5 s t adc a/d conversion time (note 4) 16 t ad t on ? st a/d on to a/d start ? . ? v~5.5v ? s 1rwh w sys sys sub sub su u s u uu u ut su uu u yu s yu u
rev. 1.00 18 ???? 0 ?? ? 01 ? rev. 1.00 19 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators op amplifer electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions d.c. characteristic v dd operating vo ? tage ? . ? 5.5 v i dd q ? iescent c ? rrent 5v no ? oad ? a1oen/a ? oen [hgwr ? 00 ? 50 a v opos i np ? t offset vo ? tage 5v -1 +1 mv i opos inp ? t offset c ? rrent v dd =5v ? v cm =1/ ? v dd ? 7d a 10 na v cm common mode vo ? tage range v ss v dd -1.4 v psrr power s ? pp ?? rejection ratio 58 80 db cmrr common mode rejection ratio v dd =5v v cm =0~v dd -1.4v 58 80 db a.c. characteristic a ol open loop gain 60 80 db sr s ? ew rate+ ? rate- no ? oad 0.01 v/s gbw gain band width r l 0 l =100pf 100k ? .5 m hz comparator electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v ddc comparator operating vo ? tage ? . ? 5.5 v i ddc comparator operating c ? rrent ? v ? 0 40 a 5v ? 0 60 a v cpos1 comparator inp ? t offset vo ? tage 5v cxof4~0=(10000) -10 +10 mv v cpos ? comparator inp ? t offset vo ? tage 5v b ? ca ? ibration -4 +4 mv v cm comparator common mode vo ? tage range v ss v dd -1.4 v aol comparator open loop gain 60 80 db t pd1 comparator response time with ? mv overdrive ? s t pd ? comparator response time with 10mv overdrive 1.5 s ldo 2.4v 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v ddin s ? pp ?? vo ? tage ? .7 5.5 v v ddout o ? tp ? t vo ? tage ? . ? 8 ? .40 ? .5 ? v i dd c ? rrent cons ? mption after start ? p ? no ? oad 50 70 a i out o ? tp ? t c ? rrent 5v v cap =1f ? 00 1100 a
rev. 1.00 18 ???? 0?? ?01? rev. 1.00 19 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators ldo 3.3v ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v ddin s ? pp ?? vo ? tage ? .6 5.5 v v ddout o ? tp ? t vo ? tage ? .1 ? ? . ? 0 ? .46 v i dd c ? rrent cons ? mption after start ? p ? no ? oad 50 70 a i out o ? tp ? t c ? rrent 5v v cap =1f ? 00 1100 a 1rwh 7klv /'? fdq surylgh vwdeoh srzhu vxsso iru ??5 vhqvru zlwk d ) fds 7kh 95() slq vkrxog eh frqqhfwhg wr ) iru ' uhihuhqfh yrowd?h dqg ) iru ??5 vhqvru power-on reset characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start vo ? tage to ens ? re power-on reset 100 mv rr vdd vdd raising rate to ens ? re power-on reset 0.0 ? 5 v/ms t por minim ? m time for vdd sta ? s at v por to ens ? re power-on reset 1 ms
rev. 1.00 ? 0 ???? 0 ?? ? 01 ? rev. 1.00 ?1 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators system architecture a key factor in the high-performanc e features of the holtek range of microcontrollers is attributed to the internal system architecture. the device take s advantage of the usual features found within risc microcontrollers providing increase d speed of operation and enhanced performance. the pipelining scheme i s i mplemented i n su ch a wa y t hat i nstruction f etching a nd i nstruction e xecution a re overlapped, hence instructions are ef fectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a crystal/ resonator or rc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? system clocking and pipelining
rev. 1.00 ?0 ???? 0?? ?01? rev. 1.00 ? 1 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is selected. however , it must be noted that only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into this register , a short program jump can be executed directly . however , as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed, it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branchin g, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section.
rev. 1.00 ?? ???? 0 ?? ? 01 ? rev. 1.00 ?? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 6 levels and is neither part of the data or program memory space, and is neither readable nor writeabl e. the activated level is indexed by the stack pointer , sp , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching.
arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 ?? ???? 0?? ?01? rev. 1.00 ?? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, th is flash device of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. structure the program memory has a capacity of 2k15 . the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within t he progra m me mory, c ertain l ocations a re re served for spe cial usa ge suc h a s re set a nd interrupts. ? location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. ? location 004h this vector is used by the external interrupt 0. if the external interrupt pin receives an active edge, t he p rogram wi ll j ump t o t his l ocation a nd b egin e xecution i f t he e xternal i nterrupt i s enabled and the stack is not full. ? location 008h this vector is us ed by the external interrupt 1. if the external interrupt pin receives an active edge, t he p rogram wi ll j ump t o t his l ocation a nd b egin e xecution i f t he e xternal i nterrupt i s enabled and the stack is not full. ? location 00ch this internal vector is used by the t imer/event counter 0. if a t imer/event counter 0 overfow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. ? location 010h this internal vector is used by the t imer/event counter 1. if a t imer/event counter 1 overfow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. ? location 014h this internal vector is used by the spi/i 2 c interrupt. when either an spi or i 2 c bus, dependent upon which one is selected, requires data transfer , the program will jump to this location and begin execution if the spi/i 2 c interrupt is enabled and the stack is not full. ? location 018h this internal vector is used by the multi-function interrupt. when the t ime base overflows, the a/d converter completes its conversion process, an active edge appears on the external peripheral i nterrupt pi n, a com parator out put i nterrupt, a n ee prom w rite or re ad c ycle ends interrupt, or a l vd detection interrupt, the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full.
rev. 1.00 ? 4 ???? 0 ?? ? 01 ? rev. 1.00 ?5 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

? ? ?? ?

? ? ?

program memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the lower order a ddress o f t he l ook u p d ata t o b e r etrieved i n t he t able p ointer r egister, t blp. t his r egister defnes the lower 8-bit address of the look-up table. after setting up the table pointer , the table data can be retrieved from the current program memory page or last program memory page using the "t abrdc[m]" or "t abrdl [m]" instructions, respectively. when these instructions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order ta ble data byte from the program mem ory wil l be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". the following diagram illustrates the addressing/data fow of the look-up table:

? ? instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc[m] pc10 pc9 pc8 @7 @6 @5 @4 @ ? @ ? @1 @0 tabrdl[m] 1 1 1 @7 @6 @5 @4 @ ? @ ? @1 @0 table location note: pc10~pc8:current program counter bits @7~@0:table pointer tblp bits
rev. 1.00 ?4 ???? 0?? ?01? rev. 1.00 ? 5 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 0700h which refers to the start address of the last page within the 2k program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 0706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the t abrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a ,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl t empreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address "0706h" transferred to tempreg1 and tblh dec t blp ; reduce value of table pointer by one tabrdl t empreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address "0705h" transferred to tempreg2 and tblh ; in this example the data "1ah" is transferred to tempreg1 and data "0fh" ; to register tempreg2 the value "00h" will be transferred to the high ; byte register tblh : : org 7 00h ; sets initial address of last page dc 00 ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 ? 6 ???? 0 ?? ? 01 ? rev. 1.00 ?7 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. programming pins function data seria ? data inp ? t/o ? tp ? t clk seria ? c ? ock res device reset vdd power s ? pp ?? vss gro ? nd the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the res pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. programmer pin mcu pins res pb6 data pa0 clk pa ? programmer and mcu pins
note: * m ay b e r esistor o r c apacitor. t he r esistance o f * m ust b e g reater t han 1 k o r t he c apacitance of * must be less than 1nf.
rev. 1.00 ?6 ???? 0?? ?01? rev. 1.00 ? 7 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored.

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? ? ? ? ? data memory structure note: most of the data memory bits can be directly manipulated using the " set [m].i" and "clr [m].i" with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers. structure divided into two sections, the frst of these is an area of ram where special function registers are located. t hese r egisters h ave fx ed l ocations a nd a re n ecessary f or c orrect o peration o f t he d evice. many of these registers can be read from and written to directly under program control, however , some remain protecte d from use r manipulation. the second area of data mem ory is reserved for general purpose use . al l l ocations wi thin t his a rea a re re ad a nd wri te a ccessible unde r progra m control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory is the address "00h". all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user program for both read and write operations. by using the "set [m].i" and "clr [m].i" instructio ns individual bits can be set or reset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory.
rev. 1.00 ? 8 ???? 0 ?? ? 01 ? rev. 1.00 ?9 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators special function registers most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section.

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? ? ???????? special purpose data memory indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointer , mp0 or mp1. acting as a pair , ia r0 w ith m p0 and ia r1 w ith m p1, can together acces s data from the d ata m emory. a s the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressi ng registers indirectl y will return a result of "00h" and writing to the registers indirectly will result in no operation.
rev. 1.00 ?8 ???? 0?? ?01? rev. 1.00 ? 9 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section " data" adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 0 0h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.00 ? 0 ???? 0 ?? ? 01 ? rev. 1.00 ?1 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators bank pointer bp the data memory is divided into two banks, known as bank 0 and bank 1. a bank pointer , which is bit 0 of the bank pointer register is used to select the required data memory bank. only data in bank 0 c an b e d irectly a ddressed a s d ata i n b ank 1 m ust b e i ndirectly a ddressed u sing me mory pointer mp1 and indirect addressing register iar1. using memory pointer mp0 and indirect addressing re gister iar0 wi ll a lways a ccess da ta from ba nk 0, i rrespective of t he va lue of t he bank pointer . memory pointer mp1 and indirect addressing register iar1 can indirectly address data in either bank 0 or bank 1 depending upon the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the idle/ sleep mode, in which case, the data memory bank remains unaf fected. it should be noted that special function data memory is not af fected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location. however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored in the program memory . tblp is the table pointer and indicates the location where the table data is located. the value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 ?0 ???? 0?? ?01? rev. 1.00 ? 1 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the interrupt routine can change the status register , precautions must be taken to correctly save it. note that bits 0~3 of the status register are both readable and writeable bits. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" ? nknown bit 7 ~ 6 unimplemented, read as "0" bit 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or " halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 ?? ???? 0 ?? ? 01 ? rev. 1.00 ?? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators eeprom data memory the ht 45f23a c ontains a n a rea o f i nternal e eprom da ta me mory eeprom, wh ich st ands for electrically erasable programmable read only memory , is by its nature a non-volatile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into mem ory space and is therefore not directly addressable in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list name bit 7 6 5 4 3 2 1 0 eea d5 d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por x x x x x x "x" ? nknown %lw a 8qlpsohphqwhg uhdg dv %lw a 'dwd ((?5?0 dgguhvv 'dwd ((?5?0 dgguhvv elw a elw
rev. 1.00 ?? ???? 0?? ?01? rev. 1.00 ?? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 %lw a 8qlpsohphqwhg uhdg dv %lw wren 'dwd ((?5?0 : ulwh (qdeoh 'lvdeoh (qdeoh 7klv lv wkh ' dwd ((? 5?0 : ulwh (qdeoh %lw z klfk pxv w eh v hw kl?k ehiruh ' dwd ((?5?0 zulwh rshudwlrqv duh fduulhg rxw ohdulq? wklv elw wr ]hur zloo lqklelw 'dwd ((?5?0 zulwh rshudwlrqv %lw wr ((?5?0 : ulwh rqwuro : ulwh ffoh kdv qlvkhg fwlydwh d zulwh ffoh 7klv l v w kh 'd wd ( (?5?0 : ulwh rqwuro % lw d qg zk hq vh w k l?k e w kh d ssolfdwlrq sur?udp zloo dfwlydwh d zulwh ffoh 7klv elw zloo eh dxwrpdwlfdoo uhvhw wr ]hur e wkh kdugzduh diwhu wkh zulwh ffoh kdv qlvkhg 6hwwlq? wklv elw kl?k zloo kdyh qr hi ihfw li wkh :5(1 kdv qrw uvw ehhq vhw kl?k %lw rden 'dwd ((?5?0 5hdg (qdeoh 'lvdeoh (qdeoh 7klv lv wkh 'dwd ((?5?0 5hdg (qdeoh %lw zklfk pxvw eh vhw kl?k ehiruh 'dwd ((?5?0 uhdg rshudwlrqv duh fduulhg rxw ohdulq? wklv elw wr ]hur z loo lqklelw ' dwd ((?5?0 uhdg rshudwlrqv %lw rd ((?5?0 5hdg rqwuro 5hdg ffoh kdv qlvkhg fwlydwh d uhdg ffoh 7klv lv wkh 'dwd ((?5?0 5hdg rqwuro %lw dqg zkhq vhw kl ?k e wkh dssolfdw lrq sur?udp zloo dfwlydwh d uhdg ffoh 7klv elw zloo eh dxwrpdwlfdoo uhvhw wr ]hur e wkh kdugzduh diwhu wkh uhdg ffoh kdv qlvkhg 6hwwlq? wklv elw kl?k zloo kdyh qr hi ihfw li wkh 5'(1 kdv qrw uvw ehhq vhw kl?k 1rwh 7kh :5(1 :5 5'(1 dqg 5' fdq qrw eh vhw wr dw wkh vdph wlph lq rqh lqvwuxfwlrq 7kh :5 dqg 5' fdq qrw eh vhw wr dw wkh vdph wlph reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he r d bi t t o de termine whe n t he da ta i s valid for reading.
rev. 1.00 ? 4 ???? 0 ?? ? 01 ? rev. 1.00 ?5 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection 3urwhfwlr djdlvw ldgyhuwhw zulwh rshudwlr lv surylghg l vhyhudo zdv iwhu wkh ghylfh lv srzhuhgr w kh ulwh ( doh lw l w kh f rwuro u hjlvwhu zl oo h f ohduhg s uhyhwlj d zu lwh rshudwlrv ovr dw srzhu r wkh dn 3rlwhu 3 zloo h uhvhw wr ]hur zklfk phdv wkdw dwd 0hpru dn zloo h vhohfwhg v wkh ((3520 frwuro uhjlvwhu lv orfdwhg l dn wklv dggv d iuwkhu phdvuh ri surwhfwlr djdlvw vsulrv zulwh rshudwlrv ulj rupdo surjudp rshudwlr hvulj wkdw wkh ulwh (doh lw l wkh frwuro uhjlvwhu lv fohduhg zloo vdihjdug djdlvw lfruuhfw zulwh rshudwlrv eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must frst be enabled by setting the ee2i bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi- function interrupt enable bit must also be set. when an eeprom write cycle ends, the e2f request ag and its associated multi-function interrupt request ag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a ump to the associated multi- function interrupt vector wi ll take place. when the interrupt is serviced only the multi-function interrupt ag will be automatically reset, the eeprom interrupt ag must be manually reset by the application program. more details can be obtained in the interrupt section. programming considerations &duh pvw h wdnh wkdw gdwd lv rw ldgyhuwhwo zulwwh wr wkh ((3520 3urwhfwlr fd h hkdfhg hvulj wkdw wkh ulwh (doh lw lv rupdoo fohduhg wr ]hur zkh rw zulwlj ovr wkh dn 3rlwhu frog h rupdoo fohduhg wr ]hur dv wklv zrog lkllw dffhvv wr dn zkhuh wkh ((3520 frwuro uhjlvwhu h[lvw owkrjk fhuwdlo rw hfhvvdu frvlghudwlr pljkw h jlyh l wkh dssolfdwlr surjudp wr wkh fkhfnlj ri wkh ydolglw ri hz zulwh gdwd d vlpsoh uhdg dfn surfhvv 7kh 5 lw l wkh ((& uhjlvwhu vkrog h vhw lpphgldwho diwhu wkh 5(1 lw lv vhw rwkhuzlvh wkh ((3520 zulwh ffoh zloo rw h h[hfwhg
rev. 1.00 ?4 ???? 0?? ?01? rev. 1.00 ? 5 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators programming examples reading data from the eeprom ? polling method mov a, ee promadres u ser d efned ad dress mov eea, a mov a, 0 40h se tup m emory p ointer m p1 mov mp1, a mp1 p oints t o e ec r egister mov a, 0 1h se tup b ank p ointer mov bp, a set iar1.1 s et r den b it, e nable r ead o perations set iar1.0 s tart r ead c ycle - s et r d b it back: 6 ,5 f khf i h d f fh h - 0 3 . 5,5 ldeh 3520 h dlh 5 3 029 h h d dd h lh 0295b7 writing data to the eeprom ? polling method mov a, ee promadres u ser d efned ad dress mov eea, a mov a, e epromdata u ser d efned da ta mov eed, a mov a, 0 40h se tup m emory p ointer m p1 mov mp1, a mp1 p oints t o e ec r egister mov a, 0 1h se tup b ank p ointer mov bp, a set iar1.3 s et w ren b it, e nable w rite o perations set iar1.2 s tart w rite c ycle - s et w r b it back: 6 ,5 f khf i lh f fh h - 0 3 . 5,5 ldeh 3520 h dlh 5 3
rev. 1.00 ? 6 ???? 0 ?? ? 01 ? rev. 1.00 ?7 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are pr ovided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions are se lected t hrough t he c onfiguration o ptions. t he hi gher fr equency o scillators pr ovide hi gher performance b ut c arry wi th i t t he d isadvantage o f h igher p ower r equirements, wh ile t he o pposite is of course true for the lower frequency osc illators. w ith the capabil ity of dynamicall y switching between fas t and s low s ystem clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins externa ? cr ? sta ? hxt 400khz~8mhz osc1/osc ? externa ? rc erc 4mhz osc1 interna ? high speed rc hirc 910khz ? ? /4/8mhz externa ? c ? ock ec 400khz~8mhz osc1 externa ? low speed cr ? sta ? lxt ?? .768khz xt1/xt ? interna ? low speed rc lirc ?? khz oscillator types 6vwhp&orfn&rjudwlrv there a re si x m ethods of genera ting t he syst em c lock, four hi gh spe ed osc illators a nd t wo l ow speed oscillators. the high speed oscillators are the external crystal/ ceramic oscillator , external rc network o scillator, e xternal c lock a nd t he i nternal 9 10khz, 2 mhz, 4 mhz o r 8 mhz r c o scillator. the t wo l ow spee d osci llators a re t he i nternal 32khz rc osci llator a nd t he e xternal 32.768khz crystal oscillator.

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rev. 1.00 ?6 ???? 0?? ?01? rev. 1.00 ? 7 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and ck s2~cks0 bits in the smo d register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators i s c hosen v ia c onfiguration o ptions. t he f requency o f t he sl ow sp eed o r h igh sp eed system clock is also determined using the hlclk bit and cks2~cks 0 bits in the smod register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. external crystal/ceramic oscillator C hxt the external crystal/ ceramic system oscillator is one of the high frequency oscillator choices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation.
? ? ?? &u\vwdo5hvrqdwru2vfloodwru+;7 crystal oscillator c1 and c2 values crystal frequency c1 c2 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note:c1 and c ? va ?? es are for g ? idance on ?? . crystal recommended capacitor values ([whudo5&2vfloodwru(5& using the erc oscillator only requires that a resistor , with a value between 56k and 2.4m, is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation fre quency; t he e xternal c apacitor has no i nfuence ove r t he fre quency a nd i s c onnected for stability purposes only . device trimming during the manufacturing process and the inclusion of i nternal f requency c ompensation c ircuits a re u sed t o e nsure t hat t he i nfluence o f t he p ower supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an exter nal 150k resistor connected and with a 5v voltage power supply and temperature of 25 ?c degrees, the oscillator will have a frequency of 4mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pc0, leaving pin pc1 free for use as a normal i/o pin.
rev. 1.00 ? 8 ???? 0 ?? ? 01 ? rev. 1.00 ?9 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators external rc oscillator C erc external oscillator C ec the system clock can also be supplied by an externally supplied clock giving users a method of synchronising t heir e xternal h ardware t o t he m icrocontroller o peration. t his i s se lected u sing a c onfiguration opt ion a nd suppl ying t he c lock on pi n osc1 . pi n osc2 shoul d be l eft fl oating if t he e xternal osc illator i s use d. t he i nternal osc illator c ircuit c ontains a fi lter c ircuit t o re duce the possi bility of e rratic ope ration due t o noise on t he osc illator pi n, howe ver a s t he fl ter c ircuit consumes a certai n amount of power , a confguration option exists to turn this flter of f. not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. internal rc oscillator C hirc 7kh lwhudo 5& rvfloodwru lv d ioo lwhjudwhg vvwhp rvfloodwru uhtlulj r h[whudo frpsrhwv 7kh l whudo 5& rvf loodwru kd v iru il [hg iuh thflhv ri h lwkhu n+] 0+] 0+] ru 0+] hylfh w ulpplj gul j w kh p didfwulj surf hvv d g w kh l fovlr ri l whudo iuhthf frpshvdwlr fluf lwv duh vhg wr hvuh wkdw wkh lhfh ri wkh srzhu vsso yrowdjh whpshudwuh dg surfhvv yduldw lrv r wkh rvfloodwlr iuhthf duh pllplvhg v d uhvow dw d srzhu vsso ri hlwkhu 9 ru 9 dg dw d whpshudwuh ri ?c degrees, the fxed oscillation freuency of 10kh, 2mh, 4m h or 8m h w ill have a tolerance w ithin 2. n ote that if this internal s ystem clock option is selected, as it reuires no external pins for its operation, i/o pins pc0 and pc1 are free for use as normal i/o pins. external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capa citor components connecte d to the 32.768khz crystal are necessary to provide oscillation. for applicati ons where precise frequencies are essential, these components may be required to provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up.
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rev. 1.00 ?8 ???? 0?? ?01? rev. 1.00 ? 9 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected i n c onsultation wi th t he c rystal o r r esonator m anufacturer?s sp ecification. t he e xternal parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/ o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. lxt oscillator c1 and c2 values crystal frequency c1 c2 ?? .768khz 10pf 10pf note:1. c1 and c ? va ?? es are for g ? idance on ?? . ? . r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values /72vfloodwru/rz3rzhufwlr the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 q ? ick start 1 low-power after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it shou ld be no ted t hat, no m atter wha t c ondition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll always function normally , the only dif ference is that it will take more time to start up if in the low- power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz a t 5 v, r equiring n o e xternal c omponents f or i ts i mplementation. de vice t rimming d uring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 ?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%.
rev. 1.00 40 ???? 0 ?? ? 01 ? rev. 1.00 41 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators supplementary oscillators the l ow spe ed osc illators, i n a ddition t o pro viding a syst em c lock sour ce a re a lso use d t o pro vide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock, c an c ome f rom e ither a h igh f requency, f h , o r l ow f requency, f l , so urce, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from either an hxt , erc, ec or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by either the lxt or lirc oscillators , selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the period t ime clock, f tbc . each of these internal clocks are sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. together with f sys /4 it is also used as one of the clock sources for the w atchdog timer . the f tb clock is used as a source for the t ime base 0/1 interrupt functions. system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power.
rev. 1.00 40 ???? 0?? ?01? rev. 1.00 41 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
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rev. 1.00 4 ? ???? 0 ?? ? 01 ? rev. 1.00 4? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the w atchdog t imer function is disabled. in this mode, the l vden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode. sleep1 mode the s leep m ode is entered w hen an h alt instruction is executed and w hen the id len bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the l vden is "1" or the w atchdog t imer function is enabled and if its clock source is chosen via confguration option to come from the f sub . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational su ch a s t he w atchdog t imer, t ime b ase 0 a nd si m. i n t he i dle0 mo de, t he sy stem oscillator will be stopped. in the id le0 mode the w atchdog t imer clock, f s , will either be on or off depending upon the f s clock source. if the source is f sys /4 then the f s clock will be of f, and if the source comes from f sub then f s will be on. idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer, t ime base 0 and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the w atchdog t imer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. control register a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is "0" 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16
rev. 1.00 4? ???? 0?? ?01? rev. 1.00 4 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast w ake-up control (only for hxt) 0: disable 1: enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f sub c lock so urce i s initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temp orary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this flag will always be read as "1" by the application program after device power -on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power .
rev. 1.00 44 ???? 0 ?? ? 01 ? rev. 1.00 45 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to re sume. t o e nsure t he de vice i s up a nd runni ng a s fa st a s possi ble a fa st w ake-up func tion i s provided, which allows f sub , namel y either the lxt or lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast w ake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/ disable function is controlled using the fsten bit in the smod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc, ec or hirc oscillator s or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the erc, ec or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. system oscillator 67(1 bit wake-up time 6/((30rgh wake-up time 6/((30rgh wake-up time ,/(0rgh wake-up time ,/(0rgh hxt 0 10 ? 4 hxt c ? c ? es 10 ? 4 hxt c ? c ? es 1~ ? hxt c ? c ? es 1 10 ? 4 hxt c ? c ? es 1~ ? f sub c ? c ? es (s ? stem r ? ns with f sub frst for 1024 hxt c ? c ? es and then switches over to r ? n with the hxt c ? ock) 1~ ? hxt c ? c ? es erc x 15~16 erc c ? c ? es 15~16 erc c ? c ? es 1~ ? erc c ? c ? es ec x 15~16 ec c ? c ? es 15~16 ec c ? c ? es 1~ ? ec c ? c ? es hirc x 15~16 hirc c ? c ? es 15~16 hirc c ? c ? es 1~ ? hirc c ? c ? es lirc x 1~ ? lirc c ? c ? es 1~ ? lirc c ? c ? es 1~ ? lirc c ? c ? es lxt x 10 ? 4 ltx c ? c ? es 10 ? 4 lxt c ? c ? es 1~ ? lxt c ? c ? es wake-up times note that if the w atchdog t imer is disabled, which means that the lxt and lirc are all both of f, then there will be no fast w ake-up function available when the device wakes-up from the sleep0 mode. operating mode switching and wake-up the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register.
rev. 1.00 44 ???? 0?? ?01? rev. 1.00 45 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the sim. the accompanying flowchart shows what happens when the device moves between the various operating modes.

? ? ?? ?

? - ? ?

? - ?

? normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the sl ow mode is sourc ed from t he lxt or the lirc osci llators and the refore requi res these oscillators to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register.
rev. 1.00 46 ???? 0 ?? ? 01 ? rev. 1.00 47 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? -?? ? ? ? ? ? ? ?- ?? ?? -? ?
? ? ? ? ? ? ?? ?? ? -?? ? ? ? ? ?? ?? ? -?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? -?? ?
rev. 1.00 46 ???? 0?? ?01? rev. 1.00 47 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110" or "111". a s a certain amount of time w ill be required for the high frequency clock to s tabilise, the status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the " halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt or l vd on. w hen t his i nstruction i s e xecuted unde r t he c onditions de scribed a bove, t he following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.00 48 ???? 0 ?? ? 01 ? rev. 1.00 49 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsson bi t in wdtc register equal to 0. when this instruction is executed under the conditions described above, the following will occur the system clock will be stopped and the application program will stop at the halt instruction, but the t ime base clock and fsub c lock w ill b e o n. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down ag, pdf, will be set and the w atchdog time-out ag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsson bit in wdtc register equal to 1. when this instruction is executed under the with conditions described above, the following will occur the system clock and t ime base clock and f sub ss suu s u 0u uu u su u u uu u u u sub u u su u su uu u u standby current considerations v wkh pdl uhdvr iru hwhulj wkh 6/((3 ru ,/( 0rgh lv wr nhhs wkh fuuhw frvpswlr ri wkh ghylfh wr dv orz d ydoh dv srvvloh shukdsv ro l wkh rughu ri vhyhudo plfurdpsv h[fhsw l wkh ,/( 0rgh wkhuh duh rwkhu frvlghudwlrv zklfk pvw dovr h wdnh lwr dffrw wkh fluflw gh vljhu l i w kh srzh u f rvpswlr l v w r h p llplvhg 6sh fldo d wwhwlr p vw h p dgh w r wkh ,2 slv r wkh ghylfh oo kljklpshgdfh lsw slv pvw h frhfwhg wr hlwkhu d [hg kljk ru orz ohyho dv d iordwlj lsw slv frog fuhdwh lwhudo rvfloodwlrv dg uhvow l lfuhdvhg fuuhw frvpswl r 7klv dovr dssolhv wr ghylfh zklfk kdyh gli ihuhw sdfndjh wshv dv wkhuh pd h rhg slv 7khvh pvw hlw khu h vhw s dv rw swv ru li vhws dv lswv pvw kdyh so okljk uhvlvwruv frhfwhg &duh p vw d ovr h w dnh zl wk w kh o rdgv zkl fk d uh f rhfwhg w r , 2 sl v zkl fk d uh vh ws d v r wswv 7khvh vkrog h sodfhg l d frglwlr l zklfk pllpp fuuhw lv gudz ru frhfwhg ro wr h[whudo fluflwv wkdw gr rw gudz fuuhw vfk dv rwkhu &026 lswv ovr rwh wkdw dgglwlrdo vwdg fuuhw zloo dovr h uhtluhg li wkh frjudwlr rswlrv kdyh hdohg wkh /7 ru /,5& rvfloodwru , wkh ,/( 0rgh wkh vvwhp rvfloodwru lv r li wkh vvwhp rvfloodwru lv iurp wkh kljk vshhg vvwhp rvfloodwru wkh dgglwlrdo vwdg fuuhw zloo dovr h shukdsv l wkh rughu ri vhyhudo kguhg plfurdpsv
rev. 1.00 48 ???? 0?? ?01? rev. 1.00 49 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system po wer-up or e xecuting t he c lear w atchdog t imer i nstructions a nd i s se t wh en e xecuting the "hal t" instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he "hal t" i nstruction. i f t he sy stem i s wo ken u p b y a n i nterrupt, t hen two p ossible si tuations m ay o ccur. t he fr st i s wh ere t he r elated i nterrupt i s d isabled o r t he i nterrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an of f state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1". a t this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source i s f rom h xt o scillator a nd f sten i s "1", the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt , tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub .
rev. 1.00 50 ???? 0 ?? ? 01 ? rev. 1.00 51 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lx t or lirc oscillators , again chosen via a confguration option. the w atchdog timer source clock is then subdivided by a ratio of 2 13 to 2 20 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with vdd, temperature and process variat ions. the lxt oscillator is supplied by an external 32.768khz crystal. the other watchdog t imer c lock so urce o ption i s t he f sys/4 clock. t he w atchdog t imer c lock so urce c an originate fr om i ts own i nternal l irc osc illator, t he l xt osc illator or fsys/ 4. it i s di vided by a value of 2 13 to 2 20 , using the ws2~ws0 bits in the wdtc register to obtain the required w atchdog timer time-out period. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 name fsyson ws ? ws1 ws0 wdten ? wdten ? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 1 0 1 0 bit 7 : f sys control in idle mode 0: disable 1: enable bit 6 ~ 4 : wdt time-out period selection 000: 2 13 /f s 001: 2 14 /f s 010: 2 15 /f s 011: 2 16 /f s 100: 2 17 /f s 101: 2 18 /f s 110: 2 19 /f s 111: 2 20 /f s these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. bit 3 ~ 0 : wdt software control 1010: disable other: enable
rev. 1.00 50 ???? 0?? ?01? rev. 1.00 51 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unkown loca tion, or enters an endless loop, these clear instruction s will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. some of the watchdog t imer options, s uch as enable/dis able, clock s ource s election and clear ins truction type are select ed using confguration options. in addition to a confguration option to enable/disable the watchdog t imer, there are also four bits, wdten3~wdten0, in the wdtc register to of fer an additional e nable/disable c ontrol o f t he w atchdog t imer. t o d isable t he w atchdog t imer, a s we ll as the confguration option being set to disable, the wdten3~wdten0 bits must also be set to a s pecifc v alue o f "1 010". any o ther v alues fo r t hese bi ts wi ll k eep t he w atchdog t imer e nabled, irrespective of the confguration enable/disable setting. after power on these bits will have the value of 1010. if the w atchdog t imer is used it is recommended that they are set to a value of 0101 for maximum noise immunity . note that if the w atchdog t imer has been disabled, then any instruction relating to its operation will result in no operation. wdt confguration option wdten3~wdten0 bits wdt wdt enab ? e xxxx enab ? e wdt disab ? e except 1010 enab ? e wdt disab ? e 1010 disab ? e :dwfkgr?7lphu(qdeoh'lvdeohrqwuro under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is an external hardware reset, which means a low level on the res pin, the second is using the w atchdog t imer software clear instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the w atchdog t imer, one of which must be chosen by confguration option. the frst option is to use the single "clr wdt" instruction while the second is to use the two commands "clr wdt1" and "clr wdt2". for the frst option, a s imple execution of " clr wd t" w ill clear the wd t w hile for the s econd option, both " clr wdt1" and "clr wdt2" must both be executed alternately to successfully clear the w atchdog timer. note that for this second option, if "clr wdt1" is used to clear the w atchdog t imer, successive executions of this instruction will have no ef fect, only the execution of a "clr wdt2" instruction will clear the w atchdog t imer. similarly after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the w atchdog t imer. the maximum time out period is when the 2 20 division ratio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 32 seconds for the 2 20 division ratio, and a minimum timeout of 250ms for the 2 13 division ration. if the f sys /4 clock is used as the w atchdog t imer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the w atchdog t imer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended.
rev. 1.00 5 ? ???? 0 ?? ? 01 ? rev. 1.00 5? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in a ddition t o t he p ower-on r eset, si tuations m ay a rise wh ere i t i s n ecessary t o f orcefully a pply a reset condition when the microcontroller is running. one example of this is where after power has be en a pplied a nd t he m icrocontroller i s a lready ru nning, t he res l ine i s fo rcefully pu lled l ow. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in dif ferent register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=100ms power-on reset timing chart 5(6 pin as the res et pin is s hared w ith p b.6, the res et function mus t be s elected us ing a configuration option. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power -on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer.
rev. 1.00 5? ???? 0?? ?01? rev. 1.00 5 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators for most applicati ons a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: "*" it is recommended that this component is added for added esd protection . "**" it is recommended that this component is added in environments where power line noise is signifcant . external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. 5(6 reset timing chart low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a confguration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally . the l vr includes the following specifcations: for a valid l vr signal, a low voltage, i.e., a voltage in the range between 0.9v~vl vr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the l vr will ignore it and will not perform a r eset f unction. on e o f a r ange o f sp ecifed v oltage v alues f or v lvr c an b e se lected u sing confguration options. note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart
rev. 1.00 54 ???? 0 ?? ? 01 ? rev. 1.00 55 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a hardware res pin reset except that the w atchdog time-out fag t o will be set to "1". note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart dwfkgrj7lphrw5hvhwgulj6/((3ru,/(0rgh the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to "0" and the t o fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during idle/sleep timing chart note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf 5(6(7&rglwlrv 0 0 power-on reset ? ? res or lvr reset d ? ring normal or slow mode operation 1 ? wdt time-o ? t reset d ? ring normal or slow mode operation 1 1 wdt time-o ? t reset d ? ring idle or sleep mode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item &rglwlriwhu5(6(7 program co ? nter reset to zero interr ? pts a ?? interr ? pts wi ?? be disab ? ed wdt c ? ear after reset ? wdt begins co ? nting timer/event co ? nter timer co ? nter wi ?? be t ? rned off inp ? t/o ? tp ? t ports i/o ports wi ?? be set ? p as inp ? ts stack pointer stack pointer wi ?? point to the top of the stack
rev. 1.00 54 ???? 0?? ?01? rev. 1.00 55 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. register power-on reset 5(6 or lvr reset wdt time-out 1rupdo2shudwlr wdt time-out ,goh6ohhs pcl 0000 0000 0000 0000 0000 0000 0000 0000 mp0 xxxx xxxx ???? ???? ???? ???? ???? ???? mp1 xxxx xxxx ???? ???? ???? ???? ???? ???? bp - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh - xxx xxxx - ??? ???? - ??? ???? - ??? ???? status - - 00 xxxx - - ?? ???? - - 1 ? ???? - - 11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - ?? - ??? intedge - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? intc0 - 000 0000 - 000 0000 - 000 0000 - ??? ???? intc1 - 000 - 000 - 000 - 000 - 000 - 000 - ??? - ??? mfic0 0000 0000 0000 0000 0000 0000 ???? ???? mfic1 - 000 - 000 - 000 - 000 - 000 - 000 - ??? - ??? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pb - 111 111 1 - 111 111 1 - 111 111 1 - ??? - ??? pbc - 111 111 1 - 111 111 1 - 111 111 1 - ??? - ??? pc - 111 111 1 - 111 111 1 - 111 111 1 - ??? - ??? pcc - 111 111 1 - 111 111 1 - 111 111 1 - ??? - ??? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pbpu - 000 0000 - 000 0000 - 000 0000 - ??? ???? pcpu - 000 0000 - 000 0000 - 000 0000 - ??? ???? pwm0 0000 0000 0000 0000 0000 0000 ???? ???? pwm1 0000 0000 0000 0000 0000 0000 ???? ???? misc 0000 - - 00 0000 - - 00 0000 - - 00 ???? - - ?? adpcr - - 00 0000 - - 00 0000 - - 00 0000 - - ?? ???? adrl xxxx - - - - xxxx - - - - xxxx - - - - ? ??? - - - - adrh xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adcr 01 - - - 000 01 - - - 000 01 - - - 000 ? ?? - - - ?? acsr 100 - - 000 100 - - 000 100 - - 000 ? ?? - - ? ?? simc0 1110 000 - 1110 000 - 1110 000 - ???? ???? simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ????
rev. 1.00 56 july 03, 2012 rev. 1.00 57 july 03, 2012 HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00 - 0 1000 00 - 0 1000 00 - 0 1000 uu - u uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1 - - - 0000 1 - - - 0000 1 - - - uuuu u - - - eea xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu lcdc - 000 0000 - 000 0000 - 000 0000 - uuu uuuu ldoc - - -0 0000 - - -0 0000 - - -0 0000 - - -u uuuu dactrl 000 - - - -0 000 - - - -0 000 - - - -0 u uu - - - -u dal 0000 - - - - 0000 - - - - 0000 - - - - uuuu - - - - dah 0000 0000 0000 0000 0000 0000 uuuu uuuu cmp1c0 0001 0000 0001 0000 0001 0000 uuuu uuuu cmp1c1 1- - - 0010 1- - - 0010 1- - - 0010 1- - - uuuu cmp2c0 0001 0000 0001 0000 0001 0000 uuuu uuuu cmp2c1 00 - - 0010 00 - - 0010 00 - - 0010 uu - - uuuu opa1c0 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - u - - - - - - - opa1c1 0000 1100 0000 1100 0000 1100 uuuu uuuu opa2c0 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - u - - - - - - - opa2c1 0000 1100 0000 1100 0000 1100 uuuu uuuu opa2c2 00 - - 0000 00 - - 0000 00 - - 0000 u u - - uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu bpctl 0000 0000 0000 0000 0000 0000 uuuu uuuu note: "-" not implemented "u" means "unchanged" "x" means "unknown"
rev. 1.00 56 ???? 0?? ?01? rev. 1.00 57 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the devic e provide bidirectional input/output lines labeled with port names p a~pc. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction "mov a,[m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 pbpu d6 d5 d4 d ? d ? d1 d0 pb d6 d5 d4 d ? d ? d1 d0 pbc d6 d5 d4 d ? d ? d1 d0 pcpu d6 d5 d4 d ? d ? d1 d0 pc d6 d5 d4 d ? d ? d1 d0 pcc d6 d5 d4 d ? d ? d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selectable via a register known as p apu, pbpu and pcpu located in the data memory . the pull-high resistors are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 papu : i/o port bit 7 ~ bit 0 pull-high control 0: disable 1: enable pbpu, pcpu register bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~0 pbpu, pcpu: i/o port bit 6 ~ bit 0 pull-high control 0: disable 1: enable
rev. 1.00 58 ???? 0 ?? ? 01 ? rev. 1.00 59 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 paw u : port a bit 7 ~ bit 0 w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~pcc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc, pcc register bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 bit 7 unimplemented, read as "0" bit 6~0 pbc, pcc: i/o port bit 6 ~ bit 0 input/output control 0: output 1: input
rev. 1.00 58 ???? 0?? ?01? rev. 1.00 59 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators port b nmos open drain control register port b pins pb0~pb3 can be setup as open drain structures. this is implemented using the ode0~ode3 bits in the misc register. misc register bit 7 6 5 4 3 2 1 0 name ode ? ode ? ode1 ode0 pfdsel pfden r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ode3 : pb3 open drain control 0: disable 1: enable bit 6 ode2 : pb2 open drain control 0: disable 1: enable bit 5 ode1 : pb1 open drain control 0: disable 1: enable bit 4 ode0 : pb0 open drain control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1~0 pfdsel, pfden : pfd related control - described elsewhere i/o pin structures the accompanying diagram illustrates the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by progra mming i ndividual bi ts i n t he port c ontrol re gister usi ng t he "se t[m].i" a nd "clr[m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
read modify write timing
rev. 1.00 60 ???? 0 ?? ? 01 ? rev. 1.00 61 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. in addition, the p ort b pins als o provide o pen d rain i/o s tructure options w hich can be controlled by the specifc register.

? ? ? ?? ? ? ?? ? ?? ? - ?? ? ?? ? - ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
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? generic input/output ports 7lphu(yhw&rwhuv the provision of timers form an important part of any microcontroller , giving the designer a means of carrying out tim e related functio ns. the device contain one 8-bit and one 16-bit count-up timer . as each timer has four dif ferent operating modes, they can be confgured to operate as a general timer, a n e xternal e vent c ounter, a n i nternal e vent c ounter for c omparator, or a s a pul se wi dth measurement device. the provision of a prescaler to the clock circuitry of the 8-bit t imer/event counter also gives added range to this timer. there are two types of registers related to the t imer/event counters. the first are the registers that contain the actual value of the t imer/event counter and into which an initial value can be preloaded. reading from these registers retrieves the contents of the t imer/event counter . the second type of associated register is the t imer control register which defnes the timer options and determines how the t imer/event counter is to be used. the t imer/event counters can have the their clock confgured to come from an internal clock source. in addition, their clock source can also be confgured to come from an external timer pin.
rev. 1.00 60 ???? 0?? ?01? rev. 1.00 61 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators confguring the timer/event counter input clock source the internal timer s clock can originate from various sources. the system clock source is used when the t imer/event counter is in the timer mode or in the pulse width measurement mode. for t imer/ event counter 0 this internal clock source is f sys y suu y u u u u 0 a u uy u u u u u u s 0 uu u u u y u suy u u s u s s u s s u u u u u s u u timer registers C tmr0, tmr1l, tmr1h 7kh wlphu uhjlvwhuv duh vshfldo ifwlr uhjlvwhuv orfdwhg l wkh 6shfldo 3usrvh dwd 0hpru dg lv wkh sodfh zkhuh wkh dfwdo wlphu ydoh lv vwruhg ru wkh lw 7 lphu(yhw &rwhu wklv uhjlvwhu lv nrz dv 705 ru lw 7lphu(yhw &rwhu wkh wlphu uhjlvwhuv duh nrz dv 705/ dg 705+ 7kh ydoh l wkh wlphu uhjlvwhuv lfuhdvhv rh hdfk wlph d lwhudo forfn sovh lv uhfhlyhg ru d h[whudo wudvlwlr rffuv r wkh h[whudo wlphu sl 7kh wlphu zloo frw iurp wkh llwldo ydoh ordghg wkh suhordg uhjlvwhu wr wkh ioo frw ri + iru wkh lw wlphu ru + iru wkh lw wlphu dw zklfk srlw wkh wlphu ryhurzv dg d lwhudo lwhuusw vljdo lv jhhudwhg 7kh wlphu ydoh zloo wkh h uhvhw zlwk wkh llwldo suhordg uhjlvwhu ydoh dg frwlh frwlj 7r dfklhyh d pd[lpp ioo udjh frw ri + iru wkh lw wlphu ru + iru wkh lw wlphu wkh suhordg uhjlvwhuv pvw uvw h fohduhg wr doo ]hurv ,w vkrog h rwhg wkdw diwhu srzhu r wkh suhordg uhjlvwhu zloo h l d nrz frglwlr 1rwh wkdw li wkh 7 lphu(yhw &rwhu lv vzlwfkhg rii dg gdwd lv zulwwh wr lwv suhordg uhjlvwhuv wklv gdwd zloo h lpphgldwho zulwwh lwr wkh dfwdo wlphu uhjlvwhuv +rzhyhu li wkh 7 lphu(yhw &rwhu lv hdohg dg frwlj d hz gdwd zulwwh lwr wkh suhordg gdwd uhjlvwhuv gulj wklv shulrg zloo uhpdl l wkh suhordg uhjlvwhuv dg zloo ro h zulwwh lwr wkh wlphu uhjlvwhuv wkh h[w wlph d ryhurz rffuv

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rev. 1.00 6 ? ???? 0 ?? ? 01 ? rev. 1.00 6? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators note: 1. the pfd clock source, pfd0 or pfd1, which is from t imer0 or t imer1, is selected by pfdsel bit in misc register. 2. the output is controlled by pa5 data. 3. cmp1x is comparator 1 output. 4. cmp2x is comparator 2 output. for the 16-bit t imer/event counter which has both low byte and high byte timer registers, accessing these registers is carried out in a specifc way . it must be noted when using instructions to preload data into the low byte timer register , namely tmr1l, the data will only be placed in a low byte buffer and not directly into the low byte timer register . the actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register , namely tmr1h, is executed. on the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte tim er register . at the same time the data in the low byte buf fer will be transferred into its associated low byte timer register . for this reason, the low byte timer register should be written frst when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register , a read to the high byte ti mer regi ster m ust be exe cuted frst t o l atch t he cont ents of the low byte t imer regi ster into its associated low byte buf fer. after this has been done, the low byte timer register can be read in the normal way . note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control registers C tmr0c, tmr1c the fexible features of the holtek microcontroller t imer/event counters enable them to operate in four dif ferent modes, the options of which are determined by the contents of their respective control register. it is the t imer control regis ter together w ith its corres ponding timer regis ters that control the full o peration o f t he t imer/event c ounters. b efore t he t imers c an b e u sed, i t i s e ssential t hat t he appropriate t imer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the four modes the timer is to operate in, either in the timer mode, the external event counting mode, the internal event counter mode, or the pulse width measurement mode, bits 7 and 6 of the t imer control register , which are known as the bit pair t0m1/t0m0 or t1m1/t1m0 respectively, depending upon which timer is used, must be set to the required logic levels. the timer- on bit, which is bit 4 of the t imer control register and known as t0on or t1on, depending upon which timer is used, provides the basic on/of f control of the respective timer . setting the bit high allows the counter to run, clearing the bit stops the counter . for timers that have prescalers, bits 0~2 of the t imer control register determ ine the division ratio of the input clock prescaler . the prescaler bit settings have no ef fect if an external clock source is used. if the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the t imer control register which is known as t0e or t1e depending upon which timer is used. an additional t1s bit in the tmr1c register is used to determin e the clock source for t imer/ event counter 1.
rev. 1.00 6? ???? 0?? ?01? rev. 1.00 6 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators confguring the timer mode in this mode, the t imer/event counter can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the t imer/event counter overows. t o operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the t imer control register must be set to the correct value as shown.control register operating mode select bits for the t imer mode bit7 bit6 1 0 ?q wklv prgh wkh lqwhuqdo forfn i sys u u uy u u sys u u uy u yu u sys u u uu y suu y u uu a u a u u u u u u u u y s 1 u 1 u u u uy u u u u uy u u yu uus u uy u u y u su uu uus u uy u uus uus u u 1 u u
timer mode timing chart confguring the event counter mode in this mode, a number of internally changing logic events, occurring on the internal comparators output, can be recorded by the t imer/event counter . t o operate in this mode, the operating mode select bit pair, t 0m1/t0m0 or t 1m1/t1m0, in the t imer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 0 0/1 ?q w klv p rgh w kh f rpsdudwru rxw sxw 0?; ru 0?; l v xvh g d v w kh 7 lphu(yhqw r xqwhu forfn vrxufh krzhyhu lw lv qrw glylghg e wkh lqwhuqdo suhvfdohu iwhu wkh rwkhu elwv lq wkh 7 lphu rqwuro 5h?lvwhu kdyh ehhq vhwxs wkh hqdeoh elw 7?1 ru 7?1 zklfk lv elw ri wkh 7 lphu rqwuro 5h?lvwhu fdq eh vhw kl?k wr hqdeoh wkh 7 lphu(yhqw rxqwhu wr uxq ?i wkh fwlyh (g?h 6hohfw elw 7( ru 7( zklfk lv elw ri wkh 7 lphu rqwuro 5h?lvwhu lv orz wkh 7 lphu(yhqw rxqwhu zloo lqfuhphqw hdfk wlph wkh h[whuqdo wlphu slq uhfhlyhv d orz wr kl?k wudqv lwlrq ?i wkh fwlyh (g?h 6 hohfw elw lv kl?k wkh frxqwhu zloo lqfuhphqw hdfk wlph wkh h[whuqdo wlphu slq uhfhlyhv d kl?k wr orz wudqvlwlrq :khq lw lv ixoo dqg ryhuiorzv dq lqwhuuxsw vl?qdo lv ?h qhudwhg dqg wkh 7 lphu(yhqw rxqwhu zloo uhordg w kh yd oxh d ouhdg o rdghg l qwr w kh suh ordg uh ?lvwhu d qg f rqwlqxh f rxqwlq? 7 kh l qwhuuxsw f dq eh glvdeohg e hqvxulq? wkdw wkh 7 lphu(yhqw rxqwhu ?qwhuuxsw (qdeoh elw lq wkh ?qwhuuxsw rqwuro 5h?lvwhu ?17 lv uhvhw wr ]hur ?w vkrxog eh qrwhg wkdw lq wkh lqwhuqdo hyhqw frxqwlq? prgh hyhq li wkh plfurfrqwuroohu lv lq wkh ?rzhu 'rzq 0rgh wkh 7 lphu(yhqw rxqwhu zloo frqwlqxh wr uhfrug h[whuqdoo fkdq?lq? or?lf hyhqwv rq wkh wlph u lqsxw slq v d uhvxow zkhq wkh wlphu ryhurzv lw zloo ?hqhudwh d wlphu lqwhuuxsw dqg fruuhvsrqglq? zdnhxs vrxufh
rev. 1.00 64 ???? 0 ?? ? 01 ? rev. 1.00 65 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
event counter mode timing chart (tne=1) confguring the pulse width measurement mode in this mode, the t imer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. t o operate in this mode, the operating mode select bit pair, t0m1/ t0m0 or t1m1/t1m0, in the t imer control register must be set to the correct value as shown. control register operating mode select bits for the pulse w idth measurement mode bit7 bit6 1 1 ?q wklv prgh wkh lqwhuqdo forfn i sys u u uy u u sys u u uy u yu u sys u u uu y suu y u uu a u a u u u u u u u u y s 1 u 1 u u u uy u yu u y uy u u s y u u u u u uy u u s 0 u 0 uy u u u u s uu u y s u u uy u s y uy u u uy u u s s u u s uu u y u u u uy u s su 0u 0 u u u u u u s uu u y u u u u u suu u u y uy u u suu uu usu s uy u u s u uu u u u s u 1 su u u u u s u s u 0 uy u u u u u s y uy u yu uus u uy u u y u su uu uus u uy u uus uus u u 1 u u u u s u s u s u su s u s y ss u u su 0 u u u s uy u 0u 0 u su u uu u s s
rev. 1.00 64 ???? 0?? ?01? rev. 1.00 65 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

? ? ? ? ??? ? ? pulse width capture mode timing chart (tne=0) programmable frequency divider pfd the programmable frequency divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. the pfd output is pin-shared with the i/o pin p a5. the pfd function is enabled via pfden bit in misc register, however, if not enabled, the pin can operate as a normal i/o pin. the clock source for the pfd circui t can originate from either the time r 0 or timer 1 overow signal selected via pfdselbit in misc register. the output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. the timer will begin to count-up from this preload register value until full, at which point an overow signal is generated, causing the pfd output to change state. the timer will then be automatically reloaded with the preload register value and continue counting-up. for the pfd output to function, it is essential that the corresponding bit of the port a control register pac bit 5 is setup as an output. if setup as an input the pfd output will not function, however , the pin can still be used as a normal input pin. the pfd output will only be activated if bit p a5 is set to 1. this output data bit is used as the on/of f control bit for the pfd output. note that the pfd output will be low if the pa5 output data bit is cleared to 0. using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated.

pfd output control
rev. 1.00 66 ???? 0 ?? ? 01 ? rev. 1.00 67 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators prescaler bits t0psc0~t0psc2 of the tmr0c register can be used to defne the pre-scaling stages of the internal clock sources of the t imer/event counter 0. the t imer/event counter overfow signal can be used to generate signals for the pfd and t imer interrupt. tmr0c register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0on t0e t0psc ? t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 bit 7~6 t0m1, t0m0 : t imer 0 operation mode selection 00: event counter mode, the input signal is from comparator 1 output 01: event counter mode, the input signal is from tc0 pin 10: timer mode 11: pulse width capture mode bit 5 unimplemented, read as "0" bit 4 t0on : t imer/event counter counting enable 0: disable 1: enable bit 3 t0e: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse w idth capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 t0psc2, t0psc1, t0psc0 : t imer prescaler rate selection timer internal clock= 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 tmr1c register bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1s t1on t1e r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 bit 7~6 t1m1, t1m0 : t imer1 operation mode selection 00: event counter mode, the input signal is from comparator 2 output 01: event counter mode, the input signal is from tc1 pin 10: timer mode 11: pulse width capture mode bit 5 t1s : timer clock source 0: f /4 1: f , lxt or lirc
rev. 1.00 66 ???? 0?? ?01? rev. 1.00 67 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators bit 4 t1on : t imer/event counter counting enable 0: disable 1: enable bit 3 t1e : event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 unimplemented, read as "0" misc register bit 7 6 5 4 3 2 1 0 name ode ? ode ? ode1 ode0 pfdsel pfden r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ode3 : pb3 open drain control 0: disable 1: enable bit 6 ode2 : pb2 open drain control 0: disable 1: enable bit 5 ode1 : pb1 open drain control 0: disable 1: enable bit 4 ode0 : pb0 open drain control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 pfdsel : pfd clock selection 0: t imer 0 output 1: t imer 1 output bit 0 pfden : pfd function control 0: pfd disable 1: pfd enable i/o interfacing the t imer/event counter , when confgured to run in the event counter or pulse width measurement mode, require the use of the external pin for correct operation. as this pin is a shared pin it must be confgured correctly to ensure it is setup for use as a t imer/event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode select bits in the t imer/event counter control regi ster, se lect ei ther t he eve nt count er or pulse wi dth m easurement m ode. addi tionally the port control register must be set high to ensure that the pin is setup as an input. any pull-high resistor on this pin will remain valid even if the pin is used as a t imer/event counter input.
rev. 1.00 68 ???? 0 ?? ? 01 ? rev. 1.00 69 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators timer/event counter pins internal filter the external t imer/event counter pins are connected to an internal flter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the exte rnal t imer/event counter input signal. as this internal flter circuit will consume a limited amount of power , a confguration option is provided to switch of f the flter function, an option whi ch m ay be be nefcial i n powe r se nsitive a pplications, but i n whi ch t he i ntegrity of t he input signal is high. care must be taken when using the flter on/of f confguration option as it will be applie d not only to both external t imer/event counter pins but also to the external interrupt input pins. individual t imer/event counter or external interrupt pins cannot be selected to have a flter on/ off function. programming considerations kh f riljuhg w r u l w kh w lphu p rgh w kh l whudo vvw hp f orfn l v vh g d v w kh w lphu f orfn vrufh dg lv wkhuhiruh vfkurlvhg zlwk wkh ryhudoo rshudwlr ri wkh plfurfrwuroohu , wklv prgh zkh wkh dssursuldwh wlphu uhjlvwhu lv ioo wkh plfurfrwuroohu zloo jhhudwh d lwhudo lwhuusw vljdo gluhfwlj wkh surjudp iorz wr wkh uhvshfwlyh lwhudo lwhuusw yhfwru ru wkh sovh zlgwk phdvuhphw prgh wkh lwhudo vvwhp forfn lv dovr vhg dv wkh wlphu forfn vrufh w wkh wlphu zloo ro u zkh wkh fruuhfw orjlf frglwlr dsshduv r wkh h[whudo wlphu lsw sl v wklv lv d h[whudo hyhw dg rw vfkurl]hg zlwk wkh lwhudo wlphu forfn wkh plfurfrwuroohu zloo ro vhh wklv h[whudo hyhw zkh wkh h[w wlphu forfn sovh duulyhv v d uhvow wkhuh pd h vpdoo gliihuhfhv l phdvuhg ydohv uhtlulj surjudpphuv wr wdnh wklv lwr dffrw gulj surjudpplj 7kh vdph dssolhv li wkh wlphu lv friljuhg wr h l wkh hyhw frwlj prgh zklfk djdl lv d h[whudo hyhw dg rw vfkurlvhg zlwk wkh lwhudo vvwhp ru wlphu forfn kh w kh 7 lphu(yhw & rwhu l v u hdg r u l i g dwd l v zu lwwh w r w kh s uhordg u hjlvwhu w kh f orfn l v l kllwhg wr dyrlg huuruv krzhyhu dv wklv pd uhvow l d frwlj huuru wklv vkrog h wdnh lwr dffrw wkh surjudpphu &duh pvw h wdnh wr hvuh wkdw wkh wlphuv duh surshuo llwldolvhg hiruh vlj wkhp iru wkh uvw wlph 7kh dvvrfldwhg wlphu hdoh lwv l wkh lwhuusw frwuro uhjlvwhu pvw h surshuo vhw rwkhuzlvh wkh lwhudo lwhuusw dvvrfldwhg zlwk wkh wlphu zloo uhpdl ldfwlyh 7kh hgjh vhohfw wlphu prgh dg forfn vrufh frwuro lwv l wlphu frwuro uhjlvwhu pvw dovr h fruuhfwo vhw wr hvuh wkh wlphu lv surshuo frjuhg iru wkh uhtluhg dssolfdwlr ,w lv dovr lpsruwdw wr hvuh wkdw d llwldo ydoh lv uvw ordghg lwr wkh wlphu uhjlvwhuv hiruh wkh wlphu lv vzlwfkhg r wklv lv hfdvh diwhu srzhu r wkh llwldo ydohv ri wkh wlphu uhjlvwhuv duh nrz iwhu wkh wlphu kdv hh llwldolvhg wkh wlphu fd h wuhg r dg ri i frwuroolj wkh hdoh lw l wkh wlphu frwuro uhjlvwhu 1rwh wkdw vhwwlj wkh wlphu hdoh lw kljk wr wu wkh wlphu r vkrog ro h h[hfwhg diwhu wkh wlphu prgh lwv kdyh hh surshuo vhws 6hwwlj wkh wlphu hdoh lw kljk wrjhwkhu zlwk d p rgh lw p rglfdwlr p d o hdg w r lpsurshu wlphu rshudwlr li h[hfwhg dv d vljoh wlphu frwuro uhjlvwhu wh zulwh lvwufwlr kh wkh 7 lphu(yhw frwhu ryhurzv lwv fruuhvsrglj lwhuusw uhthvw dj l wkh lwhuusw frwuro u hjlvwhu zl oo h vh w , i w kh w lphu l whuusw l v h dohg w klv zl oo l w u j hhudwh d l whuusw vljdo +rzhyhu luuhvshfwlyh ri zkhwkhu wkh lwhuuswv duh hdohg ru rw d 7 lphu(yhw frwhu ryhuiorz zloo dovr jhhudwh d zdnhs vljdo li wkh ghylfh lv l d 3rzhu grz frglwlr 7klv vlwdwlr pd rffu li wkh 7 lphu(yhw &rwhu lv l wkh (yhw &rwlj 0rgh dg li wkh h[whudo vljdo frwlhv wr fkdjh vwdwh , vfk d fdvh wkh 7 lphu(yhw &rwhu zloo frwlh wr frw wkhvh h[whudo hyhwv dg li d ryhurz rffuv wkh ghylfh zloo h zrnh s iurp lwv 3rzhu grz frglwlr 7 r suhyhw vfk d zdnhs iurp rffuulj wkh wlphu lwhuu sw uhthvw dj vkrog uvw h vhw kljk hiruh lvvlj wkh +/7 lvwufwlr wr hwhu wkh 3rzhu rz 0rgh
rev. 1.00 68 ???? 0?? ?01? rev. 1.00 69 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators timer program example this program example shows how the t imer/event counter registers are setup, along with how the interrupts are enabled and managed . note how the t imer/event counter is turned on, by setting bit 4 of the t imer control register . the t imer/event counter can be turned of f in a similar way by clearing the same bit. this example program sets the t imer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector org 0ch ; t imer/event c ounter 0 i nterrupt v ector jmp t mrint ; j ump h ere w hen th e t imer/event c ounter 0 o verfows : org 20h ; main program ; i nternal t imer/event c ounter 0 i nterrupt ro utine : tmrint: ; t imer/event c ounter 0 m ain p rogram p laced h ere : reti: : begin: ; setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a; mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer m ode a nd p rescaler s et to / 2 ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov intc0,a set tmr0c.4 ; s tart t imer/event c ounter 0 - n ote m ode b its m ust b e p reviously ; setup
rev. 1.00 70 ???? 0 ?? ? 01 ? rev. 1.00 71 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators pulse width modulator the ht 45f23a c ontains t wo c hannels o f 8 -bit pw m f unction. use ful f or su ch a pplications su ch as motor speed control, the pwm function provides outputs with a fxed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register. pwm operation a single register , known as pwmn and located in the data memory is assigned to each pulse w idth modulator channel. it is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output w aveform, s hould be placed. t o increas e the p wm modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode res pectively. the required mode and the on/of f control for each pwm channel is selected using the bpctl register . note that when using the pwm, it is only necessary to write the required value into the pwmn register and select the required mode setup and on/off control using the bpctl registers, the subdivision of the waveform into its sub-modulation cycles is implemented automatically w ithin the microcontroller hardware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 su b-cycles e nable t he g eneration o f h igher pw m f requencies wh ich a llow a wi der r ange o f applications to be served. the dif ference between what is known as the pwm cycle frequency and the pwm modula tion frequency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequenc y is f sys /256. however , when in the 7+1 mode of operation the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64. pwm modulation pwm cycle frequency pwm cycle duty f sys /64 for (6+ ? ) bits mode f sys /1 ? 8for (7+1) bits mode f sys / ? 56 [pwm]/ ? 56 bpctl register bit 7 6 5 4 3 2 1 0 name pmode pwm1en pwm0en bc1 bc0 bz ? bz1 bz0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : pwm type selection 0: 7+1 1: 6+2 bit 6 : pwm1 or the other pin-shared functions 0: the other pin-shared functions 1: pwm1 bit 5 : pwm0 or the other pin-shared functions 0: the other pin-shared functions 1: pwm0 bit 4~0 buzzer output and i/o confguration selection, described elsewhere
rev. 1.00 70 ???? 0?? ?01? rev. 1.00 71 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register , has 256 clock periods. however , in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter &a &w&foh mod ?? ation c ? c ? e i (i=0~ ? ) i

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6+2 pwm mode pwm register for 6+2 mode
rev. 1.00 7 ? ???? 0 ?? ? 01 ? rev. 1.00 7? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register , has 256 clock periods. however , in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit1~bit7 is denoted here as the dc value. the second group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter &a &w&foh mod ?? ation c ? c ? e i (i=0~1) i
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7+1 pwm mode pwm register for 7+1 mode
rev. 1.00 7? ???? 0?? ?01? rev. 1.00 7 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators pwm output control the pwm outputs are pin-shared with the i/o pins pc5 and pc6. t o operate as a pwm output and not as an i/o pin, the correct bits must be set in the bpctl register . a high value must be written to the pwm0en or pwm1en to select the corresponding pwm. a zero value must also be written to the corresponding bit in the i/o port control register pcc.5 and pcc.6 to ensure that the corresponding pwm output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm value has been written into the pwmn register , writing a high value to the corresponding bit in the output data register pc.5 and pc.6 will enable the pwm data to appear on the pin. w riting a zero value will disable the pwm output function and force the output low . in this way , the port data output registers can be used as an on/of f control for the pwm function. note that if the bpctl register has selected the pwm functi on, but a high value has been written to its corresponding bit in the pcc control register to confgure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options. pwm programming example the following sample program shows how the pwm0 output is setup and controlled. mov a ,64h ;setup p wm v alue o f d ecimal 1 00 mov pwm0,a clr bpctl.7 ;select the 7 +1 pw m m ode set bpctl.5 ;select pw m0 clr p cc.5 ;setup p in p c5 set p c.5 ;enable the pw m output : : clr pc.5 ; d isable the pw m output p in,pc5 f orced l ow analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the HT45F23A contains a multi-ch annel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adcr start eocb acs ? acs1 acs0 acsr adonb vrsel adcs ? adcs1 adcs0 adpcr pcr5 pcr4 pcr ? pcr ? pcr1 pcr0 'rqyhuwhu5h?lvwhu/lvw
rev. 1.00 74 ???? 0 ?? ? 01 ? rev. 1.00 75 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
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? - ? ? ??? ? ?? ? ? ??? ? ?? a/d converter structure a/d converter data registers C adrl, adrh as the device contain an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow byt e re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrh adrl 7 6 5 4 ? ? 1 0 7 6 5 4 ? ? 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d ? d ? d1 d0 0 0 0 0 a/d data registers a/d converter control registers C adcr, acsr, adpcr to control the function and operatio n of the a/d converter , three control registers known as adcr, acsr and a dpcr are provided. these 8-bit regis ters define functions such as the selection of which analog channel is connected to the internal a/d converter , the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of c onversion st atus. t he acs2~acs0 bi ts i n t he adcr re gister de fine t he adc i nput c hannel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs, which include 6 external a/d channels and 2 internal op a outputs, must be routed to the converter . it is the function of the acs2~acs0 bits to determine which analog channel input pin is actually connected to the internal a/d converter. the adpcr control register contains the pcr5~pcr0 bits which determine which pins on port b and port c are used as analog inputs for the a/d converter input and which pins are not to be used as the a /d converter input. s etting the corres ponding bit high w ill s elect the a /d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be re moved. in a ddition, a ny i nternal pu ll-high re sistors c onnected t o t hese pi ns wi ll be automatically removed if the pin is selected to be an a/d input.
rev. 1.00 74 ???? 0?? ?01? rev. 1.00 75 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators adcr register bit 7 6 5 4 3 2 1 0 name start eocb acs ? acs1 acs0 r/w r/w r r/w r/w r/w por 0 1 0 0 0 bit 7 start : start the a/d conversion 0 1 0 : start 0 1 : reset the a/d converter and set eocb to "1" this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5~3 unimplemented, read as "0" bit 2~0 acs2, acs1, acs0 : select a/d channel 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6, connect op amp 1 output (a1e) 111: an7, connect op amp 2 output (a2e) these are the a/d channel select control bits. as there is only one internal hardware a/d convert er each of the eight a/d inputs must be routed to the internal converter using these bits. acsr register bit 7 6 5 4 3 2 1 0 name adonb vrsel adcs ? adcs1 adcs0 r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 0 bit 7 unimplemented, read as "1" bit 6 adonb : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power ,even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adonb=1 before entering idle/sleep mode for saving power. 2. adonb=1 will power down the adc module.
rev. 1.00 76 ???? 0 ?? ? 01 ? rev. 1.00 77 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators bit 5 vrsel : selecte adc reference voltage 0: internal adc power 1: vref pin or ldo output (2.4v/3.3v) this bit is used to select the reference voltage for the a/d converter . if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin or ldo output ( 2.4v/3.3v).if the pin is low , then the internal reference is used which is taken from the power supply pin vdd. bit 4~3 unimplemented, read as "0" bit 2~0 adcs2, adcs1, adcs0 : select adc clock source 000: f sys /2 001: f sys /8 010: f sys /32 011: undefned 100: f sys 101: f sys /4 110: f sys /16 111: undefned these three bits are used to select the clock source for the a/d converter. adpcr register bit 7 6 5 4 3 2 1 0 name pcr5 pcr4 pcr ? pcr ? pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 pcr5 : defne pc1 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 pcr4 : defne pc0 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 pcr3 : defne pb6 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 pcr2 : defne pb5 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 pcr1 : defne pb4 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 pcr0 : defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an0
rev. 1.00 76 ???? 0?? ?01? rev. 1.00 77 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators a/d operation the st art b it i n t he adcr r egister i s u sed t o st art a nd r eset t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is comple te. this bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d int errupt request fl ag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adcs2~adcs0 bits in the acsr register. although the a/d clock source is determined by the system clock f sys , and by bits adcs2~adcs0, there a re so me l imitations o n t he m aximum a/ d c lock so urce sp eed t hat c an b e se lected. as t he minimum value of permissible a/d clock period, t adck , is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adcs2~adcs0 bits should not be set to "000". doing so will give a/d clock periods that are less than the minimum a/d clock period whi ch may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending u pon t he d evice, sp ecial c are m ust b e t aken, a s t he v alues m ay b e l ess t han t he sp ecifed minimum a/d clock period. f sys a/d clock period (t adck adcs2, adcs1, adcs0 (f sys adcs2, adcs1, adcs0 (f sys adcs2, adcs1, adcs0 (f sys adcs2, adcs1, adcs0 (f sys adcs2, adcs1, adcs0 (f sys adcs2, adcs1, adcs0 (f sys adcs2, adcs1, adcs0 1mhz 1s ? s 4s 8s 16s ?? s undefned ? mhz 500ns 1s ? s 4s 8s 16s undefned 4mhz ? 50ns* 500ns 1s ? s 4s 8s undefned 8mhz 1 ? 5ns* ? 50ns* 500ns 1s ? s 4s undefned 1 ? mhz 8 ? ns* 167ns* ??? ns* 667ns 1. ?? s ? .67s undefned a/ clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adonb bit in the acsr register . this bit must be zero to power on the a/d converter . when the adonb b it i s c leared t o z ero t o p ower o n t he a/ d c onverter i nternal c ircuitry a c ertain d elay, a s indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the pcr5~pcr0 bits in the adpcr register , if the adonb bit is zero then some power will still be consumed. in power conscious applications it is therefore recom mended that the adonb is set high to reduce power consumption when the a/d converter function is not being used.
rev. 1.00 78 ???? 0 ?? ? 01 ? rev. 1.00 79 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrsel bit. as the vref pin is pin-shared with other functions, when the vrsel bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins the a/d analog input pins are pin-shared with the i/o pins on port b and port c as well as other functions. the pcr5~ pcr0 bits in the adpcr register , determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the pcr5~ pcr0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r functi ons. al l pull -high resi stors, whi ch are se tup t hrough register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pbc or pcc port control register to enable the a/d input as when the pcr5~ pcr0 bits enable an a/d input, the status of the port control register will be overridden.

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a/d input structure the a/d converte r has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrsel bit in the acsr register. the analog input values must not be allowed to exceed the value of vref . summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adcs2~adcs0 in the acsr register. ? step 2 enable the a/d by clearing the adonb bit in the acsr register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the adcr register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the pcr5~pcr0 bits in the adpcr register.
rev. 1.00 78 ???? 0?? ?01? rev. 1.00 79 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, mulit-function interrupt bit, and the a/d converter interrupt bit, eadi, must all be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardw are will begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16t adck where t adck is equal to the a/d clock period. programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry can be switched off to reduce power consumption, by setting bit a donb high in the a csr register. when this happens, the inte rnal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a /d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
rev. 1.00 80 ???? 0 ?? ? 01 ? rev. 1.00 81 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

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rev. 1.00 80 ???? 0?? ?01? rev. 1.00 81 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example using an eocb polling method to detect the end of conversion c lr eadi ; disable adc interrupt m ov a,01h mov a csr,a ; s elect f sys /8 a s a /d cl ock ; s elect v dd a s a dc re ference v oltage a nd t urn o n adonb b it mov a ,0fh ; s etup a dpcr t o c onfgure p ins a n0~an3 mov a dpcr,a m ov a,00h mov a dcr,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr st art ; h igh p ulse o n s tart b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d polling_eoc: sz e ocb ; poll t he a dcr0 r egister e ocb b it t o d etect e nd o f a /d c onversion jmp p olling_eoc ; c ontinue p olling mov a ,adrl ; re ad l ow b yte c onversion re sult v alue mov a drl_buffer,a ; s ave r esult t o us er d efned r egister mov a ,adrh ; re ad h igh b yte c onversion re sult v alue mov a drh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp st art_conversion ; st art n ext a/d c onversion
rev. 1.00 8 ? ???? 0 ?? ? 01 ? rev. 1.00 8? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators ? example: using the interrupt method to detect the end of conversion c lr eadi ; disable adc interrupt m ov a,01h f5d h hf i 66 d f f hhf 9 d h ihhfh dh d 21 e l d k h 35 f h l 1a1 35d m ov a,00h 5d h deh d f hf 1 f kdh f hh 6dbfhl f 67 57 k lk h 67 57 e l l lldh f hl h 6 757 hh f 6 757 d f f hd l h h th d s et eadi ; enable adc interrupt h 0, h deh 0 lifl l h h 0, h deh ed l h : : ; adc interrupt service routine b df fbdfd dh h hh h d 67786 dbdfd dh 67 786 h hh h : : d 5 h d e h f hl h dh d beiihd dh h h hh hlh d 5 h d k lk e h f hl h dh d kbeiihd dh h h hh hlh : : ;,7b,17b,65 d dbdf 6 7786d hh 6 7786 i h hh h d dffbdf hh i h hh h f hd l h h th d reti
rev. 1.00 8? ???? 0?? ?01? rev. 1.00 8 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators serial interface module C sim the HT45F23A contains a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface t o external spi o r i 2 c based ha rdware suc h a s sensors, flash or e eprom memory, etc. the sim interface pins are pin-shared with pb0~pb3 pins therefore the sim interface function must frst be selected using a confguration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register . these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. spi interface the spi i nterface i s o ften u sed t o c ommunicate wi th e xternal p eripheral d evice su ch a s se nsors, flash or e eprom m emory de vice e tc. origi nally de veloped by motorola , t he four l ine spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware device. the communication is full duplex and operates as a slave/master type, where the device can be either m aster o r sl ave. al though t he spi i nterface sp ecifcation c an c ontrol m ultiple sl ave d evice from a single master , but this device provided only one scs pin. if the mas ter needs to control multiple slave device s from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared with pb0~pb3 pins and with the i 2 c function pins, the spi inter face must frst be enabled by selecting the sim enable confguration option and setting the correct bits in the simc0 and simc2 registers. after the spi confguration option has been confgured it can also be additionally disabled or enable d using the simen bit in the simc0 register . communication between devices connected to t he spi i nterface i s c arried out i n a sl ave/master m ode wi th a ll da ta t ransfer i nitiations be ing implemented by the master . the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. 63,0dvwhu6odyh&rqqhfwlrq the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol and csen bit enabled or disable select
rev. 1.00 84 ???? 0 ?? ? 01 ? rev. 1.00 85 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

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? ? ? ? ? the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are several confguration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simc0 register will have no ef fect. another two spi confguration options determine if the csen and wcol bits are to be used. spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d ? d ? d1 d0 simc ? d7 d6 ckpolb ckeg mls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown
rev. 1.00 84 ???? 0?? ?01? rev. 1.00 85 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is t imer 0 output/2 (pfd0) 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the t imer 0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: t imer 0 output/2 (pfd0) bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to hi gh and shoul d therefore be frst initiali sed by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0"
rev. 1.00 86 ???? 0 ?? ? 01 ? rev. 1.00 87 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t det ermines the base condit ion of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se condition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inactive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable /disable for the scs pin. if this bit is low , then the s cs pin will be disabled and placed into a floating condition. if the bit is high the s cs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via confguration option. bit 1 wcol : spi w rite collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cle ared by the application program. note that using the wcol bit can be disabled or enabled via confguration option. bit 0 trf : spi t ransmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set "1" automatically when an spi data transmission is complet ed, but must set to "0" by the applic ation program. it can be used to generate an interrupt.
rev. 1.00 86 ???? 0?? ?01? rev. 1.00 87 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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rev. 1.00 88 ???? 0 ?? ? 01 ? rev. 1.00 89 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

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rev. 1.00 88 ???? 0?? ?01? rev. 1.00 89 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators i 2 c interface the i 2 c interface is used to communicate with external peripheral device such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 &0dvwhu6odyhv&rhfwlr i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several confguration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. a c onfguration op tion e xists t o a llow a c lock ot her t han t he syst em c lock t o dr ive t he i 2 c interface. another confguration option determines the debounce time of the i 2 c interface. this uses the internal clock to in ef fect add a debounce time to the external cloc k to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the micro controller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface.
rev. 1.00 90 ???? 0 ?? ? 01 ? rev. 1.00 91 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d ? d ? d1 d0 sima iica6 iica5 iica4 iica ? iica ? iica1 iica0 d0 i 2 c registers list simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is t imer 0 output/2 (pfd0) 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selec tion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the t imer 0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: t imer 0 output/2 (pfd0)
rev. 1.00 90 ???? 0?? ?01? rev. 1.00 91 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators bit 1 simen : sim control 0: disable 1: enable the bi t is the overal l on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bi t changes from low to high and shoul d therefore be frst initiali sed by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the hass fag i s t he a ddress m atch fag. t his fag i s used t o de termine i f t he sla ve device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. t his fag will be "1" when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to "0" when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode
rev. 1.00 9 ? ???? 0 ?? ? 01 ? rev. 1.00 9? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesti ng to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match w ake-up control 0: disable 1: enable this bit should be set to "1" to enable i 2 c address match wake up from sleep or idle mode. bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the r xak f lag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s "0", i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determin e if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll therefore c ontinue se nding out da ta unt il t he rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica ? iica ? iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x "x" ? nknown bit 7~1 iica6~ iica0: i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~ bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program.
rev. 1.00 9? ???? 0?? ?01? rev. 1.00 9 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

? ? ? ? ? ?-? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to "1" to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the esim and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.
rev. 1.00 94 ???? 0 ?? ? 01 ? rev. 1.00 95 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

? ? ? ? ? ? - ?? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he haas bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then w rite data to the s imd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.00 94 ???? 0?? ?01? rev. 1.00 95 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 &v6odyhgguhvvfnrzohgjh6ljdo after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.00 96 ???? 0 ?? ? 01 ? rev. 1.00 97 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
? ? ? ?? ? ? ? - ?
- ? ? note: * when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram
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i 2 c bus isr flow chart
rev. 1.00 96 ???? 0?? ?01? rev. 1.00 97 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with pb4, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the t imer 0 output/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/of f control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is t imer 0 output/2 (pfd0) 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the t imer 0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: t imer 0 output/2 (pfd0) bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be first initialised by the application program. bit 0 unimplemented, read as "0"
rev. 1.00 98 ???? 0 ?? ? 01 ? rev. 1.00 99 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators scom function for lcd the device have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the pa0, pc4~pc6 pins. the lcd signals (com and seg) are generated using the application program. lcd operation an extern al lcd panel can be driven using this device by confguring the p a0 and pc4~pc6 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the lcdc register which in addition to controlling the overall on/of f function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary vdd/2 voltage levels for lcd 1/2 bias operation. the lcden bit in the lcdc register is the overall master control for the lcd driver , however this bit is used in conjunction with the comnen bits to select which i/o pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation. the following block diagram illustrates the functional structure for lcd com function. lcdbuf lcdbuf disab?e lcden comnen scom0 ~ scom? b?ffer HT45F23A lcd circuit isel lcd scom o?tp?t c?rrent generator 10?a ?5?a lcdbuf enab?e HT45F23A lcd circuit /&(1 &20(1 pin function 2wsw/hyho 0 x i/o high or low 1 0 i/o high or low 1 1 scomn vm output control
rev. 1.00 98 ???? 0?? ?01? rev. 1.00 99 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators lcd bias control the lcd com driver enables two kinds of selection to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemen ted using the isel bit in the lcdc register. lcdc register bit 7 6 5 4 3 2 1 0 name lcdbuf isel lcden com ? en com ? en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 lcdbuf : lcd buffer control bit 0: disable 1: enable bit 5 isel : scom operating current selection (v dd =5v) 0: 10a 1: 25a bit 4 lcden : lcd control bit 0: disable 1: enable the scomn can be enable by comnen if lcden=1. bit 3 com3en : pc6 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pc5 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pc4 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pa0 or scom0 selection 0: gpio 1: scom0 note: this device provides the lcd buf fer function, which is controlled by lcdbuf flag, to prevent the interference from lcd panel. w ith this buf fer, that will provide more stable reference voltages, vh0/1, vl0/1, for op a and comparator . it should be noted that if the lcd scom power supply is selected from vldo or if the lcd panel has lar ger size, than the lcd buf fer should be turned on to have a higher driver current. however , that will cause more power consumption to turn on this buffer.
rev. 1.00 100 ???? 0 ?? ? 01 ? rev. 1.00 101 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators ldo function the devic e contai n a low power voltage regulator implemented in cmos technology . using cmos technology ensures low voltage drop and low quiescent current. there are two fxed output voltages of 2.4v and 3.3v , which can be controlled by a specifc register . the internal ldo output combined with various options by register can provide a fixed voltage for the lcd bias voltage, the op a reference voltage, the adc reference voltage and as a fxed power supply for external device. ldoc register bit 7 6 5 4 3 2 1 0 name vloe ren1 vres vsel ldoen r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4 vloe : ldo output voltage control bit 0: disable 1: enable if the vloe and ldoen are set to "1", the ldo will output 2.4v or 3.3v to pin and disable i/o function. bit 3 ren1 : bias voltage divided resistor control bit 0: disable 1: enable if the ren1is set to "1", that will turn on the resistor dc path, which will generate bias voltage for opas or lcd scom. bit 2 vres : divided resistor voltage supply selection bit 0: vdd 1: vldo bit 1 vsel : ldo output voltage selection bit 0: 2.4v 1: 3.3v bit 0 ldoen : ldo control bit 0: disable 1: enable note: 1. the total resistance of the divided resistor, 500k or 200k, can be selected by the isel fag in lcdc register. 2. t o disable the ldo function will turn off the buf1 as well, no matter the ldo output voltage control bit, vloe, is enabled or not. 3. if the ldo output is as the adc reference voltage, then the vcap should be connected a 0.1f capacitor to ground. 4. if the ldo is disabled, ldoen=0, then the sw4 will be turned to vdd, no matter vres fag is "1" or not.
rev. 1.00 100 ???? 0?? ?01? rev. 1.00 101 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators the following block diagram illustrates the functional structure for ldo and divided resister. vdd vsel ldoen out ldo vdd vres vldo vloe vh1 (0.9 * vldox) vldox vh0 (0.5+1/ 16)* vldox ) vl0 (0.5-1/16 )* vldox ) vl1 (0.1* vldox ) vm (0.5* vldox ) ren1 or lcden ht45f ?? a : rtota ? = 500k or ? 00k buf1 a /d converter vdd vrsel a/ d reference vo?tage vref/ vcap sw4 vldo ?shudwlrqdopsolhuv there are two fully integrated operational amplifers in the device, op a1 and op a2. these op as can be use d for si gnal am plification ac cording t o spe cific use r requi rements. the op as ca n be disabled o r e nabled e ntirely u nder so ftware c ontrol u sing i nternal r egisters. w ith sp ecifc c ontrol registers, some op a related applications can be more fexible and easie r to be implemented, such as unit gain buffer, non-inverting amplifer , inverting amplifer and various kinds of flters, etc. operational amplifer registers the internal o perational a mplifiers are fully under the control of internal regis ters, o pa1c0, opa1c1, op a2c0, op a2c1 and op a2c2. these registers control enable/disable function, input path selection, gain control and polarity. opa1c0 register bit 7 6 5 4 3 2 1 0 name a1x r/w r por 0 bit 7 a1x : operational amplifer output; positive logic. this bit is read only. bit 6 ~0 unimplemented, read as "0"
rev. 1.00 10 ? ???? 0 ?? ? 01 ? rev. 1.00 10? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators opa1c1 register bit 7 6 5 4 3 2 1 0 name a1o ? cin a1o ? n a1psel1 a1psel0 a1ps a1ns a1oen a1en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 1 0 0 bit 7 a1o2cin : opa1 output to comparator input control bit 0: disable 1: enable bit 6 a1o2n : opa1 output to opa1 inverting input control bit 0: disable 1: enable bit 5~4 a1psel1, a1psel0 : opa1 non-inverting input selection bit 00: no connection 01: from vh1 (0.9 vldo) 10: from vm (0.5 vdd or 0.5 vldo) 11: from vl1 (0.1 vdd or 0.1 vldo) bit 3 a1ps : a1p pin to opa1 non-inverting input control bit 0: no connection 1: from a1p pin bit 2 a1ns : a1n pin to opa1 inverting input control bit 0: no connection 1: from a1n pin bit 1 a1oen : opa1 output enable or disable control bit 0: disable 1: enable note: if op a1 e nable a nd a1oe n se t t o 1, t he mcu wi ll c onsumption m ore dc power (100ua ~ 200ua). bit 0 a1en : opa1 enable or disable control bit 0: disable 1: enable opa2c0 register bit 7 6 5 4 3 2 1 0 name a ? x r/w r por 0 bit 7 a2x : operational amplifer output; positive logic. this bit is read only. bit 6 ~0 unimplemented, read as "0" opa2c1 register bit 7 6 5 4 3 2 1 0 name a ? o ? cin a ? o ? n a ? psel1 a ? psel0 a ? ps a ? ns a ? oen a ? en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 1 0 0 bit 7 a2o2cin : opa2 output to comparator input control bit 0: disable 1: enable bit 6 a2o2n : opa2 output to opa2 inverting input control bit 0: disable 1: enable
rev. 1.00 10? ???? 0?? ?01? rev. 1.00 10 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators bit 5~4 a2psel1, a2psel0 : opa2 non-inverting input selection bit 00: no connection 01: from vh1 (0.9 vldo) 10: from vm (0.5 vdd or 0.5 vldo) 11: from vl1 (0.1 vdd or 0.1 vldo) bit 3 a2ps : a2p pin to opa2 non-inverting input control bit 0: no connection 1: from a2p pin bit 2 a2ns : a2n pin to opa2 inverting input control bit 0: no connection 1: from a2n pin bit 1 a2oen : opa2 output enable or disable control bit 0: disable 1: enable note: if op a2 e nable a nd a2oe n se t t o 1, t he mcu wi ll c onsumption m ore dc power (100ua ~ 200ua). bit 0 a2en : opa2 enable or disable control bit 0: disable 1: enable opa2c2 register bit 7 6 5 4 3 2 1 0 name a1o ? a ? n a1o ? a ? p pgaen pga ? pga1 pga0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 a1o2a2n : opa1 output to opa2 inverting input control bit 0: disable 1: enable bit 6 a1o2a2p : opa1 output to opa2 non-inverting input control bit 0: disable 1: enable bit 5~4 unimplemented, read as "0" bit 3 pgaen : opa2 pga gain enable control bits 0: disable 1: enable bit 2~0 pga2, pga1, pga0 : opa2 gain control bits 000: 1 001: 8 010: 16 011: 24 100: 32 101: 40 110: 48 111: 56
rev. 1.00 104 ???? 0 ?? ? 01 ? rev. 1.00 105 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators operational amplifer operation the a dvantages o f m ultiple swi tches a nd i nput p ath o ptions, v arious r eference v oltage selection, up to 8 kinds of internal software gain control, of fset reference voltage calibration functi on and power down control for low power consumption enhance the flexibility of these two op as to suit a wide range of application possibilities. the following block diagram illustr ates the main functional blocks of the op as and comparator in this device. a? a?n a?e a1 a1n a1p vh1 vm vl1 mux 10k 560k a1ns a1o?n a?o?n r1 r? a1psel[1:0] a1x c1 c? a1ps a1oen a?x a?oen a1e a1o?a?n a1o?a?p a?p a?ns pgaen pgaen a?ps a1o?cin a?o?cin c?outen c1outen cinto c1inten c?inten c1nsel c?psel c1out c?out c1n c?p cnp cnpsel cmp1x cmp?x edge se?ect cmpes[1:0] cmpint cinto mux vh0 mux vl0 vh1 vm vl1 mux a?psel[1:0] connect an6 (a/d) connect an7 (a/d) operational amplifer functions the op as are connec ted t ogether i nternally i n a spe cifc wa y and t he output of op as ca n al so be connected to the internal comparators as shown in the block diagram. each of the op as has its own control register , with the name op a1c0, op a1c1, op a2c0, op a2c1 and op a2c2 which are used to control the enable/disable functio n, the calibration procedure and the programmable gain function of opa2. opa1 switch control 7kh iroorz lj gldjudp dg wdoh loov wudwh wkh 2 3 v zlwfk frwuro v hwwlj dg wkh fruuhv srglj frhfwlrv 1rwh wkdw vrph vzlwfk frwuro vhohfwlrv zloo irufh vrph vzlwfkhv wr h frwuroohg kdugzduh dwrpdwlfdoo ru h[dpsoh 7kh 6& lv forvhg zkh 2&,1 dg wkh 6& lv rshhg zkh 2&,1 7kh 36 zloo irufh 36(/ lh 6&6&6& zloo h rshhg kh wkh (1 6& vzlwfk duh rshhg kdugzduh wkh wkh uhodwhg ,2 slv fd h vhg dv wkh rwkhu ifwlrv
rev. 1.00 104 ???? 0?? ?01? rev. 1.00 105 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators opa1 a1e a1n a1p a1 x a1 oen cmp1 cmp2 vl1 vm vh1 opa2 a1o2 cin a1o2n a1o2a2n a1 ns a1 ps s4c s5c s6c s7c s8c s9c s 10c a1o2a2p a1ps=1 will force a1psel1,0=( 00) , i. e . s 10c, s9c , s8 c will be opened . opa1 switch control: the following table illustrates the relationship between op a1 control register settings and the switches: opa1 control bits in opa1c0, opa1c1 switch description results a1ps a1ns 36(/ 36(/ a1o2n s4c s5c s6c 6&a s10c opa1 connections 1 1 00 0 on on off off inp ? t= a1n ? a1p 0 1 01 0 off on off s10c on inp ? t= a1n ? vh1 0 1 10 0 off on off s9c on inp ? t= a1n ? vm 0 1 11 0 off on off s8c on inp ? t= a1n ? vl1 1 1 00 1 on on on off inp ? t= a1n ? a1p ? connect a1n ? a1e 1 0 00 1 on off on off inp ? t= a1p ? opa1 as ? nit gain b ? ffer 0 1 01 0 off on off s10c on inp ? t= a1n ? vh1 0 1 10 0 off on off s9c on inp ? t= a1n ? vm 0 1 11 0 off on off s8c on inp ? t= a1n ? vl1 opa1 & i/o status description: the following table illustrates the opa1 & i/o settings. a1en a1ns a1ps description 0 x x pa ? and pa ? and pa4 are i/os 1 0 0 pa ? and pa ? are i/os ? pa4 is opa1 a1e o ? tp ? t 1 0 1 pa ? is i/o. pa ? is opa1 a1p inp ? t ? pa4 is opa1 a1e o ? tp ? t 1 1 0 pa ? is i/o. pa ? is opa1 a1n inp ? t ? pa4 is opa1 a1e o ? tp ? t 1 1 1 pa ? is opa1 a1p inp ? t and pa ? is opa1 a1n inp ? t ? pa4 is opa1 a1e o ? tp ? t
rev. 1.00 106 ???? 0 ?? ? 01 ? rev. 1.00 107 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators opa2 switch control the follow ing diagram and table illus trate the o pa2 s witch control s etting and the corres ponding connections. note that some switch control selections will force some switches to be controlled by hardware automatically. for example: ? the pgaen=1 will force s6d, s7d to close and the pgaen=0 will force s6d, s7d to open. ? when the a2en=0, these switches, s6d, s7d and s9d, are opened by hardware, then the related i/o pins can be used as the other functions. opa2 a2e a2n a2p a2x a2 oen cmp1 cmp2 vl1 vm vh1 a2o2 cin a2o2n a1o2a2n opa1 10k 560 k s6d s7d s8d s9d s 10d s 11d a2 ns a2 ps s 12d s 13d s 14d s4d s5d a1o2a2p switch priority : s4 d > s 11 d > ( s 12d , s 13d , s14 d) ; if a2ps=1 , s 11d~s 14d will be opened by hardware . switch priority : s5 d > s8d ; if a2 ns=1 , s8 d will be opened by hardware . opa2 switch control: the following table illustrates the relationship between op a2 control register settings and the switches: opa2 control bits in opa2c0, opa2c1, opa2c2 switch description results a2ps a2ns 36(/ 36(/ a1o2a2p a1o2a2n 3(1 a2o2n s4d s5d s6/7d s8d s9d s11d 6a6 opa2 connections 1 1 00 0 0 0 0 on on off off off off off norma ? mode ? inp ? t = a ? n ? a ? p 0 1 01 0 0 0 0 off on off off off off s1 ? d on inp ? t = a ? n ? vh1 0 1 10 0 0 0 0 off on off off off off s1 ? d on inp ? t = a ? n ? vm 0 1 11 0 0 0 0 off on off off off off s14d on inp ? t = a ? n ? vl1 0 1 00 1 0 0 0 off on off off off on off inp ? t = a ? n ? a1e 1 0 00 0 1 0 0 on off off on off off off inp ? t = a1e ? a ? p 1 1 00 0 0 1 0 on on on off off off off inp ? t = a ? n ? a ? p 1 0 00 0 0 1 0 on off on off off off off inp ? t = a ? n ? a ? p 1 0 00 0 0 0 1 on off off off on off off inp ? t = a ? p ? opa ? as b ? ffer 0 0 01 0 0 0 1 off off off off off off s1 ? d on inp ? t = vh1 ? opa ? as b ? ffer 0 0 10 0 0 0 1 off off off off off off s1 ? d on inp ? t = vm ? opa ? as b ? ffer 0 0 11 0 0 0 1 off off off off off off s14d on inp ? t = vl1 ? opa ? as b ? ffer
rev. 1.00 106 ???? 0?? ?01? rev. 1.00 107 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators opa2 & i/o status description: the following table illustrates the opa2 & i/o settings. a2en pgaen a2ns a2ps description 0 x x x pa5 and pa6 and pa7 are i/os 1 0 0 0 pa5 and pa6 are i/os. pa7 is opa ? a ? e o ? tp ? t 1 0 0 1 pa6 is i/o. pa5 is opa ? a ? p inp ? t ? pa7 is opa ? a ? e o ? tp ? t 1 0 1 0 pa5 is i/o. pa6 is opa ? a ? n inp ? t ? pa7 is opa ? a ? e o ? tp ? t 1 0 1 1 pa5 is opa ? a ? p inp ? t and pa6 is opa ? a ? n inp ? t ? pa7 is opa ? a ? e o ? tp ? t 1 1 0 0 pa5 is i/o. pa6 is opa ? a ? n inp ? t ? pa7 is opa ? a ? e o ? tp ? t 1 1 0 1 pa5 is opa ? a ? p inp ? t and pa6 is opa ? a ? n inp ? t ? pa7 is opa ? a ? e o ? tp ? t 1 1 1 0 pa5 is i/o. pa6 is opa2 a2n input and bypass r1 (10k), pa7 is opa ? a ? e o ? tp ? t 1 1 1 1 pa5 is opa ? a ? p inp ? t and pa6 is opa ? a ? n inp ? t and b ? pass r1 (10k), pa7 is opa2 a2e output comparators two anal og comparators are contai ned within this device. these functions of fer fexibility via their register controlled features such as power -down, interrupt etc. in sharing their pins with normal i/ o pins, the comparators do not waste precious i/o pins if there functions are otherwise unused. in addition, the HT45F23A provides the calibration function to adjust the comparator offset. comparator operation the device contain two comparator functions which are used to compare two analog voltages and provide an output based on their dif ference. full control over the two internal comparators is provided via control registers, cmp1c0, cmp1c1, cmp2c0 and cmp2c1. the comparator output is recorded via a bit in their respective control register , but can also be transferred out onto a shared i/o pin or to generate an interrupt trigger with edge control function. additional comparator functions include the power down control. comparator registers the inter nal dual comparators are fully under the control of internal registers, cmp1c0, cmp1c1, cmp2c0 and cmp2c1. these registers control enable/disable function, input path selection, interrupt edge control and input offset voltage calibration function. cmp1c0 register bit 7 6 5 4 3 2 1 0 name cmp1x c1ofm c1rs c1of4 c1of ? c1of ? c1of1 c1of0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 cmp1x : comparator output; positive logic. this bit is read only. bit 6 c1ofm : comparator mode or input offset voltage cancellation mode 0: comparator mode 1: input offset voltage cancellation mode when the c1ofm=1, comparator inputs are always from i/o pins. i.e. the cnpsel and c1nsel will be forced to "1". that means disconnect the input from opas output. bit 5 c1rs : comparator input offset voltage cancellation reference selection bit 0: select c1n as the reference input 1: select cnp as the reference input bit 4~0 c1of4~c1of0 : comparator input offset voltage cancellation control bits
rev. 1.00 108 ???? 0 ?? ? 01 ? rev. 1.00 109 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators cmp1c1 register bit 7 6 5 4 3 2 1 0 name cnpsel c1inten c1outen c1nsel cmp1en r/w r/w r/w r/w r/w r/w por 1 0 0 1 0 bit 7 cnpsel : comparator non-inverting input control bit 0: from opa output 1: from cnp pin bit 6~ 4 unimplemented, read as "0" bit 3 c1inten : comparator 1 interrupt control bit 0: disable 1: enable bit 2 c1outen : comparator 1 output pin control bit 0: disable 1: enable bit 1 c1nsel : comparator 1 inverting input control bit 0: from vh0 1: from c1n pin bit 0 cmp1en : comparator 1 enable or disable control bit 0: disable 1: enable cmp2c0 register bit 7 6 5 4 3 2 1 0 name cmp ? x c ? ofm c ? rs c ? of4 c ? of ? c ? of ? c ? of1 c ? of0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 cmp2x : comparator output; positive logic. this bit is read only. bit 6 c2ofm : comparator mode or input offset voltage cancellation mode 0: comparator mode 1: input offset voltage cancellation mode when the c2ofm=1, comparator inputs are always from i/o pins. i.e. the cnpsel and c1nsel will be forced to "1". that means disconnect the input from op as output. bit 5 c2rs : operational amplifer input offset voltage cancellation reference selection bit 0: select c2p as the reference input 1: select cnp as the reference input bit 4~0 c2of4~c2of0 : comparator input offset voltage cancellation control bits
rev. 1.00 108 ???? 0?? ?01? rev. 1.00 109 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators cmp2c1 register bit 7 6 5 4 3 2 1 0 name cmpes1 cmpes0 c ? inten c ? outen c ? psel cmp ? en r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 bit 7~6 cmpes1, cmpes0 : interrupt edge control bits 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 5~4 unimplemented, read as "0" bit 3 c2inten : comparator 2 interrupt control bit 0: disable 1: enable bit 2 c2outen : comparator 2 output pin control bit 0: disable 1: enable bit 1 c2psel : comparator 2 non-inverting input control bit 0: from vl0 1: from c2p pin bit 0 cmp2en : comparator 2 enable or disable control bit 0: disable 1: enable comparator functions theses two comparators can operate together with the op as or standalone as shown in the main functional blocks of the opas and comparators. each of the intern al comparators in the HT45F23A allows for a comm on mode adjustment method of its input offset voltage. the calibration steps are as following: ? set c1ofm=1 to setup the offset cancellation mode, here s3a is closed. ? set c1rs to select which input pin is to be used as the reference voltage - s1a or s2a is closed. ? adjust c1of0~c1of4 until the output status changes. ? set c1ofm = 0 to restore the normal comparator mode. ? repeat the same procedure from steps 1 to 4 for comparator 2.
the fol lowing di agram a nd t able i llustrate t he c omparators swi tch c ontrol se tting a nd t he corresponding connections. note that some switch control selections will force some switches to be controlled by hardware automatically.
rev. 1.00 110 ???? 0 ?? ? 01 ? rev. 1.00 111 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators for example: ? when the cmp1 in calibration mode, i.e. c1ofm =1, then the sw1, sw3 will be forced to close. the cnpsel and c1nsel bits will be set "1" by hardware, and these two bits will be read out as "1". after the offset voltage calibration , the cnpsel and c1nsel will be back to its original value. ? when the cmp2 in calibration mode, i.e. c2ofm =1, then the sw1, sw2 will be forced to close. the cnpsel and c2psel bits will be set "1" by hardware, and these two bits will be read out as "1". after the offset voltage calibration, the cnpsel and c2psel will be back to its original value. ? if the cnpsel=1, the a1o2cin and a2o2cin will be forced to "0", i.e. if the swi is closed, and that will force s7c and s10d to open. ? if the cnpsel=0 and the a1o2cin=1, the a2o2cin will be forced to "0", i.e. if the s7c is closed, and that will force s10d to open.

cmp1 & i/o status description: the following table illustrates the cmp1 & i/o settings. cmp1en c1outen cnpsel c1nsel description 0 x x x pc5 and pa0 and pa1 are i/os 1 0 0 0 cnp is from opa1 or opa ? o ? tp ? t ? c1n is from vh0 inp ? t ? pa1 is i/o 1 0 0 1 cnp is from opa1 or opa ? o ? tp ? t ? c1n is from pc5 inp ? t ? pa1 is i/o 1 0 1 0 cnp is from pa0 inp ? t ? c1n is from vh0 inp ? t ? pa1 is i/o 1 0 1 1 cnp is from pa0 inp ? t ? c1n is from pc5 inp ? t ? pa1 is i/o 1 1 0 0 cnp is from opa1 or opa ? o ? tp ? t ? c1n is from vh0 inp ? t ? pa1 is comparator o ? tp ? t 1 1 0 1 cnp is from opa1 or opa ? o ? tp ? t ? c1n is from pc5 inp ? t ? pa1 is comparator o ? tp ? t 1 1 1 0 cnp is from pa0 inp ? t ? c1n is from vh0 inp ? t ? pa1 is comparator o ? tp ? t 1 1 1 1 cnp is from pa0 inp ? t ? c1n is from pc5 inp ? t ? pa1 is comparator o ? tp ? t
rev. 1.00 110 ???? 0?? ?01? rev. 1.00 111 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators cmp2 & i/o status description: the following table illustrates the cmp2 & i/o settings. cmp2en c2outen cnpsel c2psel description 0 x x x pc6 and pa0 and pa ? are i/os 1 0 0 0 cnp is from opa1 or opa ? o ? tp ? t ? c ? p is from vl0 inp ? t ? pa ? is i/o 1 0 0 1 cnp is from opa1 or opa ? o ? tp ? t ? c ? p is from pc6 inp ? t ? pa ? is i/o 1 0 1 0 cnp is from pa0 inp ? t ? c ? p is from vl0 inp ? t ? pa ? is i/o 1 0 1 1 cnp is from pa0 inp ? t ? c ? p is from pc6 inp ? t ? pa ? is i/o 1 1 0 0 cnp is from opa1 or opa ? o ? tp ? t ? c ? p is from vl0 inp ? t ? pa ? is comparator o ? tp ? t 1 1 0 1 cnp is from opa1 or opa ? o ? tp ? t ? c ? p is from pc6 inp ? t ? pa ? is comparator o ? tp ? t 1 1 1 0 cnp is from pa0 inp ? t ? c ? p is from vl0 inp ? t ? pa ? is comparator o ? tp ? t 1 1 1 1 cnp is from pa0 inp ? t ? c ? p is from pc6 inp ? t ? pa ? is comparator o ? tp ? t comparators switch control: the following table illustrates the relationship between comparators control register settings and the switches: cmp1,cmp2 control bits switch description results &136(/ &36(/ &16(/ c1ofm c1rs sw1 sw2 sw3 s1a s2a s3a s7c s10d connections 1 (forced to 1) x 1 (forced to 1) 1 1 on cnp x on c1n on off on off off inp ? t co mmon mode= cnp 1 (forced to 1) x 1 (forced to 1) 1 0 on cnp x on c1n off on on off off inp ? t common mode= c1n 1 0 1 0 x on x c1n on on off off off inp ? t = cnp ? c1n 1 0 0 0 x on x vh on on off off off inp ? t = cnp ? vh1 0 0 1 0 x off x c1n on on off on off inp ? t = a1e ? c1n 0 0 1 0 x off x c1n on on off off on inp ? t = a ? e ? c1n interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer/event counter or an a/d converter requires microcontroller attention, their corres ponding interrupt w ill enforce a temporary s uspension of the main program allowing the micro controller to direct attention to their respective needs. the device contains several external interrupt a nd i nternal i nterrupts func tions. t he e xternal i nterrupts a re c ontrolled by t he action of the external int0, int1 and pint pins, while the internal inte rrupts are controlled by the timer/event counter overfows, the t ime base interrupts, the spi/i 2 c interrupt, the a/d converter interrupt,comparator interrupt, eeprom interrupt and lvd interrupt. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the intc0, intc1, mfic0 and mfic1 registers, which are located in the data memory . by controlling the a ppropriate e nable bi ts i n t hese re gisters e ach i ndividual i nterrupt c an be e nabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. the global enable fag if cleared to zero will disable all interrupts.
rev. 1.00 11 ? ???? 0 ?? ? 01 ? rev. 1.00 11 ? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators interrupt operation a t imer/event count er ove rflow, t ime ba se 0/ 1, spi/ i 2 c da ta t ransfer c omplete, a n e nd of a/ d conversion, t he e xternal i nterrupt l ine bei ng t riggered, a c omparator out put, a n ee prom w rite or read c ycle e nds, or a l vd d etection wi ll a ll g enerate a n i nterrupt r equest b y se tting t heir corresponding request fag, if their appropriate interrupt enable bit is set. when this happens, the program counter , which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vect or. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service rout ine. here is located the code t o control t he a ppropriate i nterrupt. t he i nterrupt se rvice r outine m ust b e t erminated wi th a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however , if other interrupt requests occur during this interval, although the inter rupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurri ng in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. interrupt source priority vector externa ? interr ? pt 0 1 04h externa ? interr ? pt 1 ? 08h 7lphu(yhqwrxqwhuryhurz ? 0ch 7lphu(yhqwrxqwhuryhurz 4 10h spi/i ? c interr ? pt 5 14h m ?? ti-f ? nction interr ? pt 6 18h the a/d converter interrupt, t ime base interrupt, external peripheral interrupt, comparator interrupt, eeprom interrupt, and l vd interrupt all share the same interrupt vector which is 18h. each of t hese interrupts has their own individual interrupt fag but also share the same mff interrupt flag. the mff flag will be cleared by hardware once the multi-function interrupt is serviced, however the individual interrupts that have triggered the multifunction interrupt need to be cleared by the application program.
rev. 1.00 11 ? ???? 0?? ?01? rev. 1.00 11 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators intc0 register bit 7 6 5 4 3 2 1 0 name t0f eif1 eif0 et0i eei1 eei0 emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 t0f : t imer/event counter 0 interrupt request fag 0: inactive 1: active bit 5 eif1 : external interrupt 1 request fag 0: inactive 1: active bit 4 eif0 : external interrupt 0 request fag 0: inactive 1: active bit 3 et0i : t imer/event counter 0 interrupt enable 0: disable 1: enable bit 2 eei1 : external interrupt 1 enable 0: disable 1: enable bit 1 eei0 : external interrupt 0 enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable intc1 register bit 7 6 5 4 3 2 1 0 name mff simf t1f emfi esim et1i r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mff : multi-function interrupt request fag 0: inactive 1: active bit 5 simf : spi/i 2 c interrupt request fag 0: inactive 1: active bit 4 tif : timer/event counter 1 interrupt request fag 0: inactive 1: active bit 3 unimplemented, read as "0" bit 2 emfi : multi-function interrupt enable 0: disable 1: enable bit 1 esim : spi/i 2 c interrupt enable 0: disable 1: enable bit 0 et1i : timer/event counter 1 interrupt enable 0: disable 1: enable
rev. 1.00 114 ???? 0 ?? ? 01 ? rev. 1.00 115 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators mfic0 register bit 7 6 5 4 3 2 1 0 name pef tb1f tb0f adf epi tb1e tb0e eadi r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pef : external peripheral interrupt request fag 0: inactive 1: active bit 6 tb1f : time base 1 interrupt request fag 0: inactive 1: active bit 5 tb0f : time base 0 interrupt request fag 0: inactive 1: active bit 4 adf : a/d converter interrupt request fag 0: inactive 1: active bit 3 epi : external peripheral interrupt enable 0: disable 1: enable bit 2 tb1e : time base 1 enable 0: disable 1: enable bit 1 tb0e : time base 0 enable 0: disable 1: enable bit 0 eadi : a/d converter interrupt enable 0: disable 1: enable mfic1 register bit 7 6 5 4 3 2 1 0 name lvdf e ? f cf elvdi ee ? i eci r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 lvdf : lvd interrupt request fag 0: inactive 1: active bit 5 e2f : eeprom interrupt request fag 0: inactive 1: active bit 4 cf : comparator interrupt request fag 0: inactive 1: active bit 3 unimplemented, read as "0" bit 2 elvdi : lvd interrupt enable 0: disable 1: enable bit 1 ee2i : eeprom interrupt enable 0: disable 1: enable bit 0 eci : comparator interrupt enable 0: disable 1: enable
rev. 1.00 114 ???? 0?? ?01? rev. 1.00 115 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request ags, eif0~eif1, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, eei0~eei1, must first be set. additionally the correct interrupt edge type mus t be s elected us ing the in tedge regis ter to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subrout ine c all t o the e xternal i nterrupt ve ctor, wi ll t ake pl ace. w hen t he i nterrupt i s se rviced, the external interr upt request ags, eif0~eif1, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the intedge register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the intedge register can also be used to disable the external interrupt function.

rev. 1.00 116 ???? 0 ?? ? 01 ? rev. 1.00 117 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators
? ? ? ?
? ? ? ? ? ? - ?? ? ? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ? ?? ? ? ?
? ? ? ?? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? ? ?? ? ? ? ? ? interrupt structure the external interrupt pins are connected to an internal flter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal. as this internal flter circuit will consume a limited amount of power , a confguration option is provided to switch of f the flter function, an option which may be benefcial in power sensitive applications, but in which the integrity of the input signal is high. care must be taken when using the flter on/of f confguration option as it will be applied not only to both the external interrupt pins but also to the timer/event counter external input pins. individual external interrupt or t imer/event counter pins cannot be selected to have a flter on/off function.
rev. 1.00 116 ???? 0?? ?01? rev. 1.00 117 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators intedge register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 %lw a xqlpsohphqwhg uhdg dv 0 a int1s1, int1s0 ,17 (gh vhohfw glvdeoh ulvl hgh wulhu idool hgh wulhu gxdo hgh wulhu lw a int0s1, int0s0 ,170 u uu uu uu external peripheral interrupt the exte rnal peripheral interrupt operates in a similar way to the exter nal interrupt and is contained within the multi-function interrupt. for an external peripheral interrupt to occur , the global interrupt enable bit, emi, external peripheral interrupt enable bit, epi, and multi-function interrupt enable bit, emfi, must frst be set. an actual external peripheral interrupt will take place when the external interrupt request ag, pef , is set, a situation that will occur when a negative transition, appears on the pint pin. the external peripheral interrupt pin is pin-shared with the i/o pin pb5, and is confgured as a peripheral interrupt pin via a u s uus y u type ssu u sus u uus s u 0 uus yu s u susu uus uy 0 u u uus yu 0 uus ut u u u ss suu timer/event counter interrupt for a t imer/event counter interrupt to occur , the global interrupt enable bit, emi, and the corresponding time r interrupt enable bi t, et0i or et1i, must fi rst be set. an actual t imer/event counter interrupt will take place when the t imer/event counter request ag, t0f or t1f , is set, a situation that will occur when the t imer/event counter overows. when the interrupt is enabled, the stack is not full and a t imer/event counter overow occurs, a subroutine call to the timer interrupt vector at location 0ch or 10h, will take place. when the interrupt is serviced, the timer interrupt request ag, t0f or t1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. spi/i 2 c interface interrupt ru d 63,, & lwhuusw wr rffu wkh jordo lwhuusw hdoh lw (0, dg wkh fruuhvsrglj lwhuusw hdoh lw (6,0 pvw h uvw vhw dfwdo 63,, & lwhuusw zloo wdnh sodfh zkh wkh 63,, & lwhuidfh uhthvw dj 6,0 lv vhw d vlwdwlr wkdw zloo rffu zkh d wh ri gdwd kdv hh wudvplwwhg ru uhfhlyhg wkh 63,, & lwhuidfh kh wkh lwhuusw lv hdohg wkh vwdfn lv rw ioo dg d wh ri gdwd kdv hh wudvplwwhg ru uhfhlyhg wkh 63,, & lwh uidfh d vurwlh fdoo wr wkh 63,, & lwhuusw yhfwru dw orfdwlr + zloo wdnh sodfh kh wkh lwhuusw lv vhuylfhg wkh 63, , & uhthvw dj 6,0 zloo h dwrpdwlfdoo uhvhw dg wkh (0, lw zloo h dwrpdwlfdoo fohduhg wr glvdoh rwkhu lwhuuswv
rev. 1.00 118 ???? 0 ?? ? 01 ? rev. 1.00 119 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators multi-function interrupt an additional interrupt known as the multi-function interrupt is provided. unlike the other interrupts, this interrupt has no independent source, but rather is formed from four other existing interrupt sources, namely the a/d converter interrupt, t ime base interrupts, the external peripheral interrupt, comparator interrupt, eeprom interrupt and lvd interrupt. for a multi-function interrupt to occur , the global interrupt enable bit, emi, and the multi-function interrupt enable bit, emfi, must frst be set. an actual multi-function interrupt will take place when the multi-function interrupt request flag, mff , is set. this will occur when either a t ime base overflow, an a/d conversion completion, an external peripheral interrupt, a comparator output interrupt, an eeprom w rite or read cycle ends interrupt, or a l vd interrupt is generated. when the interrupt is enabled and the stack is not full, and either one of the interrupts contained within the multi-function interrupt occurs, a subroutine call to the multi-function interrupt vector at location 018h will take place. when the interrupt is serviced, the multi-function request flag, mff , will be automatically reset and the emi bit will be aut omatically cleared to di sable other interrupts. however, it m ust be not ed t hat t he re quest fl ags from t he ori ginal sourc e of t he mul ti-function interrupt, namely the t ime-base interrupt, a/d converter interrupt or external peripheral interrupt will not be automatically reset and must be manually reset by the application program. a/d interrupt the a/d interrupt is contained within the multi-function interrupt. for a n a/ d in terrupt t o b e g enerated, t he g lobal i nterrupt e nable b it, e mi, a/ d in terrupt e nable bit, eadi, and multi-function inter rupt enable bit, emfi, must frst be set. an actual a/d interrupt will take pl ace whe n t he a/ d int errupt re quest fa g, adf , i s se t, a si tuation t hat wi ll oc cur whe n the a/ d conversion proc ess ha s fni shed. w hen t he i nterrupt i s e nabled, t he st ack i s not ful l a nd the a/ d conversion p rocess h as e nded, a su broutine c all t o t he mu lti-function i nterrupt v ector a t location18h, will t ake pl ace. w hen t he a/ d int errupt i s se rviced, t he e mi bi t wi ll be c leared t o disable other interrupts, however only the mff interrupt request fag will be reset. as the adf fag will not be automatically reset, it has to be cleared by the application program. time base interrupt the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time bas e overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.00 118 july 03, 2012 rev. 1.00 119 july 03, 2012 HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators

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time base interrupt tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tbon: tb0 and tb1 control 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp: lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb comparator interrupt the comparator interrupt is contained within the multi-function interrupt. the comparator interrupt is controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request fag, cf, is set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, eci , must frst be set. when the interrupt is enabled, the stack is not full and the comparator input generates a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the comparator interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automatically cleared. as the cf fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.00 1 ? 0 ???? 0 ?? ? 01 ? rev. 1.00 1?1 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators eeprominterrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request ag, e2f , is set, which occurs when an eeprom w rite or r ead c ycle ends. t o allow t he program to b ranch to i ts re spective interrupt vector address, the global interrupt enable bit, emi, eeprom interrupt enable bit, ee2i, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite or read cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request ag will be also automatically cleared. as the e2f ag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt 7kh / rz 9 rowdjh h whfwru , whuusw l v f rwdlhg zl wkl w kh 0 owlifwlr , whuusw / 9 ,whuusw uhthvw zloo wdnh sodfh zkh wkh / 9 ,whuusw uhthvw dj / 9 lv vhw zklfk rffuv zkh wkh /rz 9 rowdjh hwhfwru ifwlr ghwhfwv d orz srzhu vsso yrowdjh 7 r doorz wkh surjudp wr udfk wr lwv uhvshfwlyh lwhuusw yhfwru dgguhvv wkh jordo lwhuusw hdoh lw (0, /rz 9 rowdjh ,whuusw hdoh lw (/ 9, dg dvvrfldwhg 0owlifwlr lwhuusw hdoh lw pvw uvw h vhw kh wkh lwhuusw lv hdohg wkh vwdfn lv rw ioo dg d orz yrowdjh frglwlr rffuv d vurwlh fdoo wr wkh 0owlifwlr ,whuusw yhfwru zloo wdnh sodfh kh wkh /rz 9 rowdjh ,whuusw lv vhuylfhg w kh ( 0, lw zl oo h d wrpdwlfdoo f ohduhg w r gl vdoh rw khu l whuuswv kr zhyhu r o w kh 0owlifwlr lwhuusw uhthvw dj zloo h dovr dwrpdwlfdoo fohduhg v wkh / 9 dj zloo rw h dwrpdwlfdoo fohduhg lw kdv wr h fohduhg wkh dssolfdwlr surjudp interrupt wake-up function (dfk ri wkh lw huusw ifw lrv kdv wkh fdsd lolw ri zdnl j s wkh pl furfrwuroohu zkh l wkh 6/((3 ru ,/( 0rgh zdnhs lv jhhudwhg zkh d lwhuusw uhthvw dj fkdjhv iurp orz wr kljk dg lv lghshghw ri zkhwkhu wkh lwhuusw lv hdohg ru rw 7khuhiruh hyh wkrjk wkh ghylfh lv l wkh 6/((3 ru ,/( 0rgh dg lwv vvwhp rvfloodwru vwrsshg vlwdwlrv vfk dv h[whudo hgjh wudvlwlrv r wkh h [whudo l whuusw s lv d o rz s rzhu v sso y rowdjh r u f rpsdudwru l sw f kdjh pd fdvh wkhlu uhvshfwlyh lwhuusw dj wr h vhw kljk dg frvhthw o jhhudwh d lwhuusw &duh pvw wkhuhiruh h wdnh li vsulrv zdnhs vlwdwlrv duh wr h dyrlghg ,i d lwhuusw zdnhs ifwlr lv wr h glvdohg wkh wkh fruuhvsrglj lwhuusw uhthvw dj vkrog h vhw kljk hiruh wkh ghylfh hwhuv wkh 6/((3 ru ,/( 0rgh 7kh lwhuusw hdoh lwv kdyh r hi ihfw r wkh lwhuusw zdnhs ifwlr programming considerations glvdolj wkh lwhuusw hdoh lwv d uhthvwhg lwhuusw fd h suhyhwhg iurp hlj vhuylfhg krzhyhu rfh d l whuusw uh thvw d j l v vh w l w zl oo uh pdl l w klv f rglwlr l w kh ,17 & ,17 & 0,& d g 0,& uhjlvwhuv wlo wkh fruuhvsrglj lwhuusw lv vhuylfhg ru wlo wkh uhthvw dj lv fohduhg wkh dssolfdwlr surjudp ,w lv uhfrpphghg wkdw surjudpv gr rw vh wkh &// 6urwlh lvwufwlr zlwkl wkh lwhuusw vurwlh ,whuuswv riwh rffu l d suhglfwdoh pdhu ru hhg wr h vhuylfhg lpphgldwho in ss uus u u u t u uus u uus y s s suu u 0 uu u s u u uu u u uus uy suu uus u u t y y
rev. 1.00 1?0 ???? 0?? ?01? rev. 1.00 1 ? 1 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators buzzer operating in a similar way to the programmable frequency divider , the buzzer function provides a means o f p roducing a v ariable f requency o utput, su itable f or a pplications su ch a s pi ezo-buzzer driving or ot her e xternal c ircuits t hat re quire a pre cise fre quency ge nerator. t he bz a nd bz pi ns form a complimentary pa ir, a nd a re pi n-shared wi th i/ o pi ns, p a6 a nd p a7. a bpct l re gister i s used to select from one of three buzzer options. the frst option is for both pins p a6 and p a7 to be used as normal i/os, the second option is for both pins to be confgured as bz and bz buzzer pins, the third option selects only the p a6 pin to be used as a bz buzzer pin with the p a7 pin retaining its normal i/o pin function. note that the bz pin is the inverse of the bz pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the internal clock source, f tb , which then passes through a divider , the division ratio of which is selected by bpctl register to provide a range of buzzer frequencies from f tb /2 2 to f tb /2 9 . the clock source that generates f tb , which in turn controls the buzzer frequency , can originate from three dif ferent sources, the lxt oscillator , the lirc oscillator or the system oscillator/4, the choice of which is determined by the f tb clock source option. note that the buzzer frequency is controlled by bpctl register, which select the source clock for the internal clock f tb .
? ? ?? ? ?- ? ?? ? ? buzzer function if the bpctl options have selected both pins p a6 and p a7 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operatio n it is essential that both pins must be set up a s outputs by set ting bi ts p ac6 a nd p ac7 of t he p ac port c ontrol re gister t o z ero. the pa6 data bit in the pa data register must also be set high to enable the buzzer outputs, if set low, both pins p a6 and p a7 will remain low . in this way the single bit p a6 of the p a register can be used as an on/of f control for both the bz and bz buzzer pin outputs. note that the p a7 data bit in the p a register has no control over the bz buzzer pin pa7. bpctl register bit 7 6 5 4 3 2 1 0 name pmode pwm0en pwm1en bc1 bc0 bz ? bz1 bz0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 pwm control bits bit 4~3 bc1~bc0 : buzzer or i/o 00: pa7 is i/o, pa6 is i/o 01: pa7 is i/o, pa6 is bz 10: reserved 11: pa7 is bz , pa6 is bz bit 2~0 bz2~bz0 : buzzer output frequency selection 000: f tb /2 2 001: f tb /2 3 010: f tb /2 4 011: f tb /2 5 100: f tb /2 6 101: f tb /2 7 110: f tb /2 8 111: f tb /2 9
rev. 1.00 1 ?? ???? 0 ?? ? 01 ? rev. 1.00 1?? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators pa6/pa7 pin function control pac register pac6 pac register pac7 pa data register pa6 pa data register pa7 output function 0 0 1 pa6=bz pa7= bz 0 0 0 pa6= "0" pa7= "0" 0 1 1 pa6=bz pa7=inp ? t ? ine 0 1 0 pa6= "0" pa7=inp ? t ? ine 1 0 d pa6=inp ? t ? ine pa7= d 1 1 pa6=inp ? t ? ine pa7=inp ? t ? ine "x" stands for dont care "d" stands for data "0" or "1" if the options have selected that only the p a6 pin is to function as a bz buzzer pin, then the p a7 pin can be used as a normal i/o pin. for the p a6 pin to function as a bz buzzer pin, p a6 must be setup as an output by setting bit p ac6 of the p ac port control register to zero. the p a6 data bit in the p a data register must also be set high to enable the buzzer output, if set low pin p a6 will remain low . in this way the p a6 bit can be used as an on/of f control for the bz buzze r pin p a6. if the p ac6 bit of the pac port control register is set high, then pin p a6 can still be used as an input even though the option has confgured it as a bz buzzer output. note that no matter what bpctl option is chosen for the buzzer , if the port control register has setup the pin to function as an input, then this will override the bpctl option selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the bpctl option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit.

buzzer output pin control note: the above drawing shows the situation where both pins pa6 and pa7 are selected by bpctl option to be bz and bz buzzer pin outputs. the port control register of both pins must have already been setup as output. the data setup on pin pa7 has no effect on the buzzer outputs.
rev. 1.00 1?? ???? 0?? ?01? rev. 1.00 1 ?? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators power down mode and wake-up entering the idle or sleep mode there i s on ly on e wa y f or t he de vice t o e nter t he sl eep o r i dle mo de a nd t hat i s t o e xecute t he halt instruction in the application program. when this instruction is executed, the following will occur the system clock will be stopped and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub u s u u u su u su uu u u standby current considerations v wkh pdl uhdvr iru hwhulj wkh 6/((3 ru ,/( 0rgh lv wr nhhs wkh fuuhw frvpswlr ri wkh ghylfh wr dv orz d ydoh dv srvvloh shukdsv ro l wkh rughu ri vhyhudo plfurdpsv wkhuh duh rwkhu frvlghudwlrv zklf k p vw do vr h wd nh lw r df frw wkh fl uflw ghvl jhu l i w kh srzhu frvpswlr lv wr h pllplvhg 6shfldo dwwhwlr pvw h pdgh wr wkh ,2 slv r wkh ghylfh oo kljklpshgdfh lsw slv pvw h frhfwhg wr hlwkhu d [hg kljk ru orz ohyho dv d rdwlj lsw slv frog fuhdwh lwhudo rvfloodwlrv dg uhvow l lfuhdvhg fuuhw frvpswlr 7klv dovr dssolhv wr ghylfh zklfk kdyh gli ihuhw sdfndjh wshv dv wkhuh pd h rhg slv 7khvh pvw hlwkhu h vhws dv rwswv ru li vhws dv lswv pvw kdyh sookljk uhvlvwruv frhfwhg &duh pvw dovr h wdnh zlwk wkh ordgv zklfk duh frhfwhg wr ,2 slv zklfk duh vhws dv rwswv 7khvh vkrog h sodfhg l d frglwlr l zklfk pllpp fuuhw lv gudz ru frhfwhg ro wr h[whudo fluflwv wkdw gr rw gudz fuuhw vfk dv rwkhu &026 lswv ovr rwh wkdw dgglwlrdo vwdg fuuhw zloo dovr h uhtluhg li wkh frjudwlr rswlrv kdyh hdohg wkh /,5& rvfloodwru wake-up iwhu wkh vvwhp hwhuv wkh 6/((3 ru ,/( 0rgh lw fd h zrnh s iurp rh ri ydulrv vrufhv olvwhg dv iroorzv h[whudo uhvhw h[whudo idoolj hgjh r 3ruw vvwhp lwhuusw 7 ryhurz ,i wkh vvwhp lv zrnh s d h[whudo uhvhw wkh ghylfh zloo h[shulhfh d ioo vvwhp uhvhw krzhyhu li wkh ghylfh lv zrnh s d 7 ryhurz d dwfkgrj 7 lphu uhvhw zloo h llwldwhg owkrjk rwk ri wkhvh zdnhs phwkrgv zloo llwldwh d uhvhw rshudwlr wkh dfwdo vrufh ri wkh zdnhs fd h ghwhuplhg h[dpllj wkh 7 2 dg 3 iodjv 7kh 3 iodj lv fohduhg d vvwhp srzhu s ru h[hfwlj wkh fohdu dwfkgrj 7 lphu lvwufwlrv dg lv vhw zkh h[hfwlj wkh +/7 lvwufwlr 7kh 7 2 dj lv vhw li d 7 wlphrw rffuv dg fdvhv d zdnhs wkdw ro uhvhwv wkh 3urjudp &rwhu dg 6wdfn 3rlwhu wkh rwkhu djv uhpdl l wkhlu ruljldo vwdwv (dfk sl r 3ruw fd h vhws vlj wkh 3 8 uhjlvwhu wr shuplw d hjdwlyh wudvlwlr r wkh sl wr zdnhs wkh vvwhp kh d 3ruw sl zdnhs rffuv wkh surjudp zloo uhvph h[hfwlr dw wkh lvwufwlr iroorzlj wkh +/7 lvwufwlr
rev. 1.00 1 ? 4 ???? 0 ?? ? 01 ? rev. 1.00 1?5 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators if the system is woken up by an inte rrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when t he r elated i nterrupt i s f inally e nabled o r wh en a st ack l evel b ecomes f ree. t he o ther situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. low voltage detector C lvd this de vice ha s a l ow v oltage de tector func tion, a lso known a s l vd. t his e nabled t he de vice t o monitor the power supply voltage, vdd, and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be detem ined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the vdd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: n o low v oltage detect 1: low v oltage detect bit 4 lvden : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 lvd2~lvd0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100 : 3.0v 101: 3.3v 110: 3.6v 111: 4.4v
rev. 1.00 1?4 ???? 0?? ?01? rev. 1.00 1 ? 5 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.4v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit l vdo transitions. the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vdf inte rrupt request fag will be set, causing an int errupt to be generated if vdd fall s below the pre set l vd vol tage. this wil l cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the l vdf fag should be frst set high before the device enters the sleep or idle mode. lvd operation
rev. 1.00 1 ? 6 ???? 0 ?? ? 01 ? rev. 1.00 1?7 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators voice output voice control the voice control register controls the dac circuit. if the dac circuit is not enabled, any dah/ dal outputs will be invalid. w riting a "1" to the dacen bit will enable the dac circuit and channel the dac output to its corresponding i/o pin, while writing a "0" to the dacen bit will disable the dac circuit. audio output and volume control C dal, dah, dactrl the audio output is 12-bits wide whose highest 8-bits are written into the dah register and whose lowest four bits are written into the highest four bits of the dal register . bits 0~3 of the dal register are always read as zero. there a re 8 l evels of volum e whi ch a re set up usi ng t he dact rl re gister. t he hi ghest 3-bi ts of this register are used for volume control and the dacen bit is used to control the dac function enable or not. once the dacen bit is set to "1", this will channel the dac output to the i/o pin and disable the original i/o pin shared function.

dactrl register bit 7 6 5 4 3 2 1 0 name vol ? vol1 vol0 dacen r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~5 vol2~vol0 : dac volume control data bit 4~1 unimplemented, read as "0" bit 0 dacen : dac enable control bit 0: disable 1: enable note: when the dacen is set to "1", the dac signal will be channeled to the i/o pin anddisable the original i/o pin shared function.
rev. 1.00 1?6 ???? 0?? ?01? rev. 1.00 1 ? 7 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators confguration options confguration options refer to certain options within the mcu that are programmed into the otp program memory device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device us ing the hardw are programming tools, once they are s elected they can not be changed later by the application software. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 osc t ? pe se ? ection: erc or cr ? sta ? or hirc or ec (externa ? c ? ock) 00 . hxt (fi ? ter on) 01 . erc (fi ? ter on) 10. hirc (fi ? ter off) 11. ec (fi ? ter off) ? low speed s ? stem osci ?? ator se ? ection-f l : lxt ? lirc ? hirc freq ? enc ? se ? ection: 4mhz ? 910khz ? ? mhz ? 8mhz 4 f s c ? ock se ? ection: f sub or f sys /4 5 hxt mode se ? ection: 455khz or 1m~8mhz watchdog options 6 wdt enab ? e or disab ? e 7 clrwdt instr ? ctions: 1 or ? instr ? ctions lvr/lvd options 8 lvr f ? nction: enab ? e or disab ? e 9 lvr vo ? tage : ? .1v or ? .55v or ? .15v or 4. ? v rc filter 10 rc flter for tmr0/1 & int0/1, enable or disable spi 11 sim enab ? e/disab ? e 1 ? spi_wcol: enab ? e/disab ? e 1 ? spi_csen: enab ? e/disab ? e ? ? sed to enab ? e/disab ? e (1/0) software csen f ? nction i 2 c 14 i ? c debo ? nce time: no debo ? nce ? 1 s ? stem c ? ock ? ? s ? stem c ? ock res 15 i/o or res f ? nction: lock options 16 lock a ?? 17 partia ? lock
rev. 1.00 1 ? 8 ???? 0 ?? ? 01 ? rev. 1.00 1?9 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators application circuits

rev. 1.00 1?8 ???? 0?? ?01? rev. 1.00 1 ? 9 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 1 ? 0 ???? 0 ?? ? 01 ? rev. 1.00 1?1 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 1?0 ???? 0?? ?01? rev. 1.00 1 ? 1 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data memor ? to acc 1 z ? c ? ac ? ov addm a ? [m] add acc to data memor ? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data memor ? to acc with carr ? 1 z ? c ? ac ? ov adcm a ? [m] add acc to data memor ? with carr ? 1 note z ? c ? ac ? ov sub a ? x s ? btract immediate data from the acc 1 z ? c ? ac ? ov sub a ? [m] s ? btract data memor ? from acc 1 z ? c ? ac ? ov subm a ? [m] s ? btract data memor ? from acc with res ?? t in data memor ? 1 note z ? c ? ac ? ov sbc a ? [m] s ? btract data memor ? from acc with carr ? 1 z ? c ? ac ? ov sbcm a ? [m] s ? btract data memor ? from acc with carr ?? res ?? t in data memor ? 1 note z ? c ? ac ? ov daa [m] decima ? adj ? st acc for addition with res ?? t in data memor ? 1 note c logic operation and a ? [m] logica ? and data memor ? to acc 1 z or a ? [m] logica ? or data memor ? to acc 1 z xor a ? [m] logica ? xor data memor ? to acc 1 z andm a ? [m] logica ? and acc to data memor ? 1 note z orm a ? [m] logica ? or acc to data memor ? 1 note z xorm a ? [m] logica ? xor acc to data memor ? 1 note z and a ? x logica ? and immediate data to acc 1 z or a ? x logica ? or immediate data to acc 1 z xor a ? x logica ? xor immediate data to acc 1 z cpl [m] comp ? ement data memor ? 1 note z cpla [m] comp ? ement data memor ? with res ?? t in acc 1 z increment & decrement inca [m] increment data memor ? with res ?? t in acc 1 z inc [m] increment data memor ? 1 note z deca [m] decrement data memor ? with res ?? t in acc 1 z dec [m] decrement data memor ? 1 note z rotate rra [m] rotate data memor ? right with res ?? t in acc 1 none rr [m] rotate data memor ? right 1 note none rrca [m] rotate data memor ? right thro ? gh carr ? with res ?? t in acc 1 c rrc [m] rotate data memor ? right thro ? gh carr ? 1 note c rla [m] rotate data memor ? ? eft with res ?? t in acc 1 none rl [m] rotate data memor ? ? eft 1 note none rlca [m] rotate data memor ? ? eft thro ? gh carr ? with res ?? t in acc 1 c rlc [m] rotate data memor ? ? eft thro ? gh carr ? 1 note c
rev. 1.00 1 ?? ???? 0 ?? ? 01 ? rev. 1.00 1?? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators mnemonic description cycles flag affected data move mov a ? [m] move data memor ? to acc 1 none mov [m] ? a move acc to data memor ? 1 note none mov a ? x move immediate data to acc 1 none bit operation clr [m].i c ? ear bit of data memor ? 1 note none set [m].i set bit of data memor ? 1 note none branch ? mp addr ?? mp ? nconditiona ??? ? none sz [m] skip if data memor ? is zero 1 note none sza [m] skip if data memor ? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memor ? is zero 1 note none snz [m].i skip if bit i of data memor ? is not zero 1 note none siz [m] skip if increment data memor ? is zero 1 note none sdz [m] skip if decrement data memor ? is zero 1 note none siza [m] skip if increment data memor ? is zero with res ?? t in acc 1 note none sdza [m] skip if decrement data memor ? is zero with res ?? t in acc 1 note none call addr s ? bro ? tine ca ?? ? none ret ret ? rn from s ? bro ? tine ? none ret a ? x ret ? rn from s ? bro ? tine and ? oad immediate data to acc ? none reti ret ? rn from interr ? pt ? none table read tabrdc [m] read tab ? e to tblh and data memor ? ? note none tabrdl [m] read tab ? e ( ? ast page) to tblh and data memor ? ? note none miscellaneous nop no operation 1 none clr [m] c ? ear data memor ? 1 note none set [m] set data memor ? 1 note none clr wdt c ? ear watchdog timer 1 to ? pdf clr wdt1 pre-c ? ear watchdog timer 1 to ? pdf clr wdt ? pre-c ? ear watchdog timer 1 to ? pdf swap [m] swap nibb ? es of data memor ? 1 note none swapa [m] swap nibb ? es of data memor ? with res ?? t in acc 1 none halt enter power down mode 1 to ? pdf 1rwh )ru vnls lqvwuxfwlrqv li wkh uhvxow ri wkh frpsdulvrq lqyroyhv d vnls wkhq wzr ffohv duh uhtxluhg li qr vnls wdnhv sodfh rqo rqh ffoh lv uhtxluhg q lqvwuxfwlrq zklfk fkdq?hv wkh frqwhqwv ri wkh ?/ zloo dovr uhtxluh ffohv iru h[hfxwlrq ) ru wkh /5 :' 7 dqg /5 :' 7 lqv wuxfwlrqv wkh 7 ? dqg ? ') iod?v pd eh di ihfwhg e wkh h[hfxwlrq vwdwxv 7kh 7 ? dqg ?') iod?v duh fohduhg diwhu erwk /5 :'7 dqg /5 :'7 lqvwuxfwlrqv duh frqvhfxwlyho h[hfxwhg ?wkhuzlvh wkh 7 ? dqg ?') d?v uhpdlq xqfkdq?hg
rev. 1.00 1?? ???? 0?? ?01? rev. 1.00 1 ?? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators instruction defnition adc a,[m] gg dwd 0 hpru wr && z lwk &duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru ffpodwru d g w kh f duu dj d uh d gghg 7kh uh vow lv v wruhg l w kh ffpodwru 2shudwlr && 8 && p & iihfwhg djv 29 & & adcm a,[m] gg && wr dwd 0 hpru z lwk &duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru ffpodwru d g w kh f duu dj d uh d gghg 7kh uh vow lv v wruhg l w kh vs hflhg dwd 0 hpru 2shudwlr p 8 && p & iihfwhg djv 29 & & add a,[m] gg dwd 0 hpru w r && hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh ffpodwru d uh d gghg 7kh uh vow lv v wruhg l w kh ffpodwru 2shudwlr && 8 && p iihfwhg djv 29 & & add a,x gg lp phgldwh gdwd wr hvfulswlr 7kh f rwhwv r i w kh ffxpxodwru d g w kh v shflhg lp phgldwh gdwd d uh d gghg 7kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr 8 iihfwhg dv 29 = addm a,[m] gg && wr dwd 0 hpru hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh ffpodwru d uh d gghg 7kh uh vow lv v wruhg l w kh vs hflhg dwd 0 hpru 2shudwlr p 8 && p iihfwhg djv 29 & & and a,[m] /rjlfdo 1 dwd 0 hpru w r && hvfulswlr dwd l w kh ffpodwru d g w kh v shflhg dwd 0 hpru s huirup d lwzlvh o rjlfdo 1 rshudwlr 7 kh uh vow lv v wruhg l w kh ffpodwru 2shudwlr && 8 && 1 p iihfwhg djv and a,x rlfdo 1 lp phgldwh gdwd wr hvfulswlr dwd l w kh ffxpxodwru d g w kh v shflhg lp phgldwh gdwd s huirup d e lw z lvh o rlfdo 1 rshudwlr 7 kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr 8 1 iihfwhg dv = andm a,[m] /rjlfdo 1 && wr dwd 0 hpru hvfulswlr dwd l w kh v shflhg dwd 0 hpru d g w kh ffpodwru s huirup d lwzlvh o rjlfdo 1 rshudwlr 7 kh uh vow lv v wruhg l w kh dwd 0 hpru 2shudwlr p 8 && 1 p iihfwhg djv
rev. 1.00 1 ? 4 ???? 0 ?? ? 01 ? rev. 1.00 1?5 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.00 1?4 ???? 0?? ?01? rev. 1.00 1 ? 5 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.00 1 ? 6 ???? 0 ?? ? 01 ? rev. 1.00 1?7 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.00 1?6 ???? 0?? ?01? rev. 1.00 1 ? 7 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected ag(s) none rl [m] 5rwdwh dwd 0 hpru o hiw hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d uh u rwdwhg o hiw lw z lwk lw u rwdwhg l wr lw 2shudwlr pl 8 pl l a p 8 p iihfwhg djv 1rh rla [m] 5rwdwh dwd 0 hpru ohiw z lwk uh vxow l hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d uh u rwdwhg o hiw e e lw z lwk e lw u rwdwhg l wr e lw 7kh u rwdwhg u hvxow l v v wruhg l w kh ffxpxodwru d g w kh f rwhwv r i w kh dwd 0 hpru u hpdl x fkdhg 2shudwlr l 8 > pl l a 8 > p iihfwhg dv 1rh rlc [m] 5rwdwh dwd 0 hpru o hiw w kurxk duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh f duu d d uh u rwdwhg o hiw e e lw lw uhsodfhv w kh duu e lw d g w kh r ulldo f duu d l v u rwdwhg l wr e lw 2shudwlr >pl 8 > pl l a >p 8 8 > p iihfwhg dv rlca [m] 5rwdwh dwd 0 hpru ohiw w kurjk & duu z lwk uh vow l && hvfulswlr dwd l w kh v shflhg dwd 0 hpru dg w kh fduu dj duh u rwdwhg o hiw lw lw u hsodfhv w kh &duu lw d g w kh r uljldo f duu dj l v u rwdwhg l wr w kh lw 7k h u rwdwhg u hvow l v v wruhg l w kh ffpodwru d g w kh f rwhwv r i w kh dwd 0 hpru u hpdl fkdjhg 2shudwlr &&l 8 pl l a && 8 & & 8 p iihfwhg djv & rr [m] 5rwdwh dwd 0 hpru u lkw hvfulswlr 7kh frwhwv ri w kh v shflhg dwd 0 hpru duh u rwdwhg u lkw e e lw z lwk e lw u rwdwhg l wr e lw 2shudwlr >pl 8 > pl l a >p 8 > p iihfwhg dv 1rh
rev. 1.00 1 ? 8 ???? 0 ?? ? 01 ? rev. 1.00 1?9 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.00 1?8 ???? 0?? ?01? rev. 1.00 1 ? 9 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.00 140 ???? 0 ?? ? 01 ? rev. 1.00 141 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.00 140 ???? 0?? ?01? rev. 1.00 141 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.00 14 ? ???? 0 ?? ? 01 ? rev. 1.00 14? ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.157 c 0.01 ? D 0.0 ? 0 c ? 0. ? 86 D 0.40 ? d D D 0.069 e D 0.050 D f 0.004 D 0.010 g 0.016 D 0.050 h 0.007 D 0.010 0? D 8? symbol dimensions in mm min. nom. max. a 5.79 D 6. ? 0 b ? .81 D ? .99 c 0. ? 0 D 0.51 c ? 9.80 D 10. ? 1 d D D 1.75 e D 1. ? 7 D f 0.10 D 0. ? 5 g 0.41 D 1. ? 7 h 0.18 D 0. ? 5 0? D 8?
rev. 1.00 14? ???? 0?? ?01? rev. 1.00 14 ? ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.158 c 0.008 0.01 ? c 0. ?? 5 0. ? 47 d 0.049 0.065 e 0.0 ? 5 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 . 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 4.01 c 0. ? 0 0. ? 0 c 8.51 8.81 d 1. ? 4 1.65 e 0.64 f 0.10 0. ? 5 g 0. ? 8 1. ? 7 h 0.18 0. ? 5 . 0 8
rev. 1.00 144 ???? 0 ?? ? 01 ? rev. 1.00 145 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0. ?? 5 0. ? 46 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 . 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 8.51 8.79 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 . 0 8
rev. 1.00 144 ???? 0?? ?01? rev. 1.00 145 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators product tape and reel specifcations reel dimensions 16-pin nsop (150mil) symbol description dimensions in mm a ree ? o ? ter diameter ?? 0.01.0 b ree ? inner diameter 100.01.5 c spind ? e ho ? e diameter 1 ? .0 +0.5/-0. ? d ke ? s ? it width ? .00.5 t1 space between f ? ang 16.8 +0. ? /-0. ? t ? ree ? thickness ?? . ? 0. ? 20-pin ssop (150mil) symbol description dimensions in mm a ree ? o ? ter diameter ?? 0.01.0 b ree ? inner diameter 100.01.5 c spind ? e ho ? e diameter 1 ? .0 +0.5/-0. ? d ke ? s ? it width ? .00.5 t1 space between f ? ang 16.8 +0. ? /-0. ? t ? ree ? thickness ?? . ? 0. ? 24-pin ssop (150mil) symbol description dimensions in mm a ree ? o ? ter diameter ?? 0.01.0 b ree ? inner diameter 100.01.5 c spind ? e ho ? e diameter 1 ? .0 +0.5/-0. ? d ke ? s ? it width ? .00.5 t1 space between f ? ang 16.8 +0. ? /-0. ? t ? ree ? thickness ?? . ? 0. ?
rev. 1.00 146 ???? 0 ?? ? 01 ? rev. 1.00 147 ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators carrier tape dimensions

16-pin nsop (150mil) symbol description dimensions in mm w carrier tape width 16.00. ? p cavit ? pitch 8.00.1 e perforation position 1.750.10 f cavit ? to perforation(width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavit ? ho ? e diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation(length direction) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 10. ? 0.1 k0 cavit ? depth ? .10.1 t carrier tape thickness 0. ? 00.05 c cover tape width 1 ? . ? 0.1 20-pin ssop (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0. ? /-0.1 p cavit ? pitch 8.00.1 e perforation position 1.750.10 f cavit ? to perforation(width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit ? ho ? e diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation(length direction) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 9.00.1 k0 cavit ? depth ? . ? 0.1 t carrier tape thickness 0. ? 00.05 c cover tape width 1 ? . ? 0.1
rev. 1.00 146 ???? 0?? ?01? rev. 1.00 147 ???? 0 ?? ? 01 ? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators 24-pin ssop (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0. ? /-0.1 p cavit ? pitch 8.00.1 e perforation position 1.750.10 f cavit ? to perforation(width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit ? ho ? e diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation(length direction) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 9.50.1 k0 cavit ? depth ? .10.1 t carrier tape thickness 0. ? 00.05 c cover tape width 1 ? . ? 0.1
rev. 1.00 148 ???? 0 ?? ? 01 ? rev. 1.00 pb ???? 0?? ?01? HT45F23A 8-bit flash mcu with op amps & comparators HT45F23A 8-bit flash mcu with op amps & comparators holtek semiconductor inc. (headquarters) no. ?? creation rd. ii ? science park ? hsinch ?? taiwan te ? : 886- ? -56 ? -1999 fax: 886- ? -56 ? -1189 http://www.ho ? tek.com.tw holtek semiconductor inc. (taipei sales offce) 4f- ?? no. ? - ?? y ? anq ? st. ? nankang software park ? taipei 115 ? taiwan te ? : 886- ? - ? 655-7070 fax: 886- ? - ? 655-7 ? 7 ? fax: 886- ? - ? 655-7 ? 8 ? (internationa ? sa ? es hot ? ine) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a ? prod ? ctivit ? b ? i ? ding ? no.5 gaoxin m ? nd road ? nanshan district ? shenzhen ? china 518057 te ? : 86-755-8616-9908 ? 86-755-8616-9 ? 08 fax: 86-755-8616-97 ?? holtek semiconductor (usa), inc. (north america sales offce) 467 ? 9 fremont b ? vd. ? fremont ? ca 945 ? 8 ? usa te ? : 1-510- ? 5 ? -9880 fax: 1-510- ? 5 ? -9885 http://www.ho ? tek.com cop ? right ? ? 01 ? b ? holtek semiconductor inc. the information appearing in this data sheet is be ? ieved to be acc ? rate at the time of p ? b ? ication. however ? ho ? tek ass ? mes no responsibi ? it ? ar ising from the ? se of the specifications described. the app ? ications mentioned herein are ? sed so ? e ?? for the p ? rpose of i ??? stration and ho ? tek makes no warrant ? or representation that s ? ch app ? ications wi ?? be s ? itab ? e witho ? t f ? rther modification ? nor recommends the ? se of its prod ? cts for app ? ication that ma ? present a risk to h ? man ? ife d ? e to ma ? f ? nction or otherwise. ho ? tek's prod ? cts are not a ? thorized for ? se as critica ? components in ? ife vxssruwghylfhvruvvwhpv+rowhnuhvhuyhvwkhul?kwwrdowhulwvsurgxfwvzlwkrxwsulruqrwlfdwlrq)ru the most ? p-to-date information ? p ? ease visit o ? r web site at http://www.ho ? tek.com.tw .

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